Add support for the AR9285 chipset, which is found on many netbooks
available today. This card is a low power 802.11bgn that only does 11n rates up to MCS 7 (that's 65 Mbps in 20Mhz mode and 135 in 40Mhz mode). 802.11n is not yet supported, but will be in the future. The driver still has a problem regarding to the setting of txpower on the card, so don't expect good performance yet. After fixing this problem, an MFC is possible. Special thanks to iXsystems and S Smirnov <tonve at yandex.ru> for help with the purchase of a netbook with this card. Sponsored by: iXsystems, Inc.
This commit is contained in:
Rui Paulo
parent
b0a5caf4f2
commit
f3d3bf8731
@ -554,6 +554,9 @@ dev/ath/ath_hal/ah_eeprom_v3.c optional ath_hal | ath_ar5211 | ath_ar5212 \
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dev/ath/ath_hal/ah_eeprom_v14.c \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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compile-with "${NORMAL_C} -I$S/dev/ath"
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dev/ath/ath_hal/ah_eeprom_v4k.c \
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optional ath_hal | ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath"
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dev/ath/ath_hal/ah_regdomain.c optional ath \
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compile-with "${NORMAL_C} -I$S/dev/ath"
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# ar5210
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@ -600,104 +603,119 @@ dev/ath/ath_hal/ar5211/ar5211_xmit.c optional ath_hal | ath_ar5211 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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# ar5212
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dev/ath/ath_hal/ar5212/ar5212_ani.c \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
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ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5212/ar5212_attach.c \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
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ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5212/ar5212_beacon.c \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
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ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5212/ar5212_eeprom.c \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
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ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5212/ar5212_gpio.c \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
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ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5212/ar5212_interrupts.c \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
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ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5212/ar5212_keycache.c \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
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ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5212/ar5212_misc.c \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
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ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5212/ar5212_phy.c \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
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ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5212/ar5212_power.c \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
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ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5212/ar5212_recv.c \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
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ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5212/ar5212_reset.c \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
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ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5212/ar5212_rfgain.c \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
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ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5212/ar5212_xmit.c \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \
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ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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# ar5416 (depends on ar5212)
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dev/ath/ath_hal/ar5416/ar5416_ani.c \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5416/ar5416_attach.c \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5416/ar5416_beacon.c \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5416/ar5416_cal.c \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5416/ar5416_cal_iq.c \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5416/ar5416_eeprom.c \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5416/ar5416_gpio.c \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5416/ar5416_interrupts.c \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5416/ar5416_keycache.c \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5416/ar5416_misc.c \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5416/ar5416_phy.c \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5416/ar5416_power.c \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5416/ar5416_recv.c \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5416/ar5416_reset.c \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5416/ar5416_xmit.c \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 \
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optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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# ar9160 (depends on ar5416)
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dev/ath/ath_hal/ar5416/ar9160_attach.c optional ath_hal | ath_ar9160 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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# ar9280 (depends on ar5416)
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dev/ath/ath_hal/ar5416/ar9280_attach.c optional ath_hal | ath_ar9280 \
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# ar9280/ar9285 (depends on ar5416)
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dev/ath/ath_hal/ar5416/ar9280_attach.c optional ath_hal | ath_ar9280 | \
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ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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# rf backends
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dev/ath/ath_hal/ar5212/ar2316.c optional ath_rf2316 \
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@ -716,7 +734,7 @@ dev/ath/ath_hal/ar5212/ar5413.c optional ath_hal | ath_rf5413 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5416/ar2133.c optional ath_hal | ath_ar5416 | ath_ar9160 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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dev/ath/ath_hal/ar5416/ar9280.c optional ath_hal | ath_ar9280 \
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dev/ath/ath_hal/ar5416/ar9280.c optional ath_hal | ath_ar9280 | ath_ar9285 \
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compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal"
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# ath rate control algorithms
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dev/ath/ath_rate/amrr/amrr.c optional ath_rate_amrr \
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@ -39,8 +39,6 @@
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#define AR5416_4K_NUM_CTLS 12
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#define AR5416_4K_NUM_BAND_EDGES 4
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#define AR5416_4K_NUM_PD_GAINS 2
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#define AR5416_4K_PD_GAINS_IN_MASK 4
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#define AR5416_4K_PD_GAIN_ICEPTS 5
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#define AR5416_4K_MAX_CHAINS 1
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/*
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@ -127,8 +125,8 @@ typedef struct CalCtlData4k {
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} __packed CAL_CTL_DATA_4K;
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typedef struct calDataPerFreq4k {
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uint8_t pwrPdg[AR5416_4K_NUM_PD_GAINS][AR5416_4K_PD_GAIN_ICEPTS];
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uint8_t vpdPdg[AR5416_4K_NUM_PD_GAINS][AR5416_4K_PD_GAIN_ICEPTS];
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uint8_t pwrPdg[AR5416_4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
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uint8_t vpdPdg[AR5416_4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
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} __packed CAL_DATA_PER_FREQ_4K;
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struct ar5416eeprom_4k {
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@ -14,7 +14,7 @@
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $Id: ar5212_power.c,v 1.4 2008/11/10 04:08:03 sam Exp $
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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@ -38,8 +38,8 @@ static HAL_BOOL
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ar5212SetPowerModeAwake(struct ath_hal *ah, int setChip)
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{
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#define AR_SCR_MASK \
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(AR_SCR_SLDUR|AR_SCR_SLE|AR_SCR_SLE|AR_SCR_SLDTP|AR_SCR_SLDWP|\
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AR_SCR_SLEPOL|AR_SCR_MIBIE)
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(AR_SCR_SLDUR|AR_SCR_SLE|AR_SCR_SLDTP|AR_SCR_SLDWP|\
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AR_SCR_SLEPOL|AR_SCR_MIBIE|AR_SCR_UNKNOWN)
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#define POWER_UP_TIME 2000
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uint32_t scr, val;
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int i;
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@ -700,6 +700,7 @@
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#define AR_SCR_SLDWP 0x00080000 /* sleep duration write policy */
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#define AR_SCR_SLEPOL 0x00100000 /* sleep policy mode */
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#define AR_SCR_MIBIE 0x00200000 /* sleep perf cntrs MIB intr ena */
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#define AR_SCR_UNKNOWN 0x00400000
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#define AR_INTPEND_TRUE 0x00000001 /* interrupt pending */
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@ -44,6 +44,7 @@ typedef struct {
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#define AR5416_CCA_MAX_GOOD_VALUE -85
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#define AR5416_CCA_MAX_HIGH_VALUE -62
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#define AR5416_CCA_MIN_BAD_VALUE -140
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#define AR9285_CCA_MAX_GOOD_VALUE -118
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#define AR5416_SPUR_RSSI_THRESH 40
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@ -183,7 +183,7 @@ ar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
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if (level >= params->maxNoiseImmunityLevel) {
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: level out of range (%u > %u)\n",
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"%s: immunity level out of range (%u > %u)\n",
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__func__, level, params->maxNoiseImmunityLevel);
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return AH_FALSE;
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}
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@ -267,7 +267,7 @@ ar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
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if (level >= params->maxFirstepLevel) {
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: level out of range (%u > %u)\n",
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"%s: firstep level out of range (%u > %u)\n",
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__func__, level, params->maxFirstepLevel);
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return AH_FALSE;
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}
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@ -285,7 +285,7 @@ ar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
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if (level >= params->maxSpurImmunityLevel) {
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: level out of range (%u > %u)\n",
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"%s: spur immunity level out of range (%u > %u)\n",
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__func__, level, params->maxSpurImmunityLevel);
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return AH_FALSE;
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}
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@ -352,7 +352,7 @@ ar5416Attach(uint16_t devid, HAL_SOFTC sc,
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}
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ar5416AniSetup(ah); /* Anti Noise Immunity */
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ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
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ar5416InitNfHistBuff(ah, AH5416(ah)->ah_cal.nfCalHist);
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HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
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@ -173,7 +173,59 @@ ar5416InitCal(struct ath_hal *ah, const struct ieee80211_channel *chan)
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ichan = ath_hal_checkchannel(ah, chan);
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HALASSERT(ichan != AH_NULL);
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if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
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if (AR_SREV_KITE_12_OR_LATER(ah)) {
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/* Clear the carrier leak cal bit */
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OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
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||||
|
||||
if (IEEE80211_IS_CHAN_HT20(chan)) {
|
||||
OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL,
|
||||
AR_PHY_PARALLEL_CAL_ENABLE);
|
||||
OS_REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
|
||||
OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
|
||||
AR_PHY_AGC_CONTROL_FLTR_CAL);
|
||||
OS_REG_CLR_BIT(ah, AR_PHY_TPCRG1,
|
||||
AR_PHY_TPCRG1_PD_CAL_ENABLE);
|
||||
OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
|
||||
AR_PHY_AGC_CONTROL_CAL);
|
||||
/* Poll for offset calibration complete */
|
||||
if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL,
|
||||
AR_PHY_AGC_CONTROL_CAL, 0)) {
|
||||
HALDEBUG(ah, HAL_DEBUG_ANY,
|
||||
"%s: offset calibration failed to "
|
||||
"complete in 1ms; noisy environment?\n",
|
||||
__func__);
|
||||
return AH_FALSE;
|
||||
}
|
||||
OS_REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
|
||||
OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
|
||||
AR_PHY_PARALLEL_CAL_ENABLE);
|
||||
}
|
||||
OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
|
||||
|
||||
/* Enable Rx Filter Cal */
|
||||
OS_REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
|
||||
OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
|
||||
AR_PHY_AGC_CONTROL_FLTR_CAL);
|
||||
OS_REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
|
||||
|
||||
/* kick off the cal */
|
||||
OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
|
||||
|
||||
/* Poll for offset calibration complete */
|
||||
if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL,
|
||||
AR_PHY_AGC_CONTROL_CAL, 0)) {
|
||||
HALDEBUG(ah, HAL_DEBUG_ANY,
|
||||
"%s: offset calibration did not complete in 1ms; "
|
||||
"noisy environment?\n", __func__);
|
||||
return AH_FALSE;
|
||||
}
|
||||
/* Set the cl cal bit and rerun the cal a 2nd time */
|
||||
/* Enable Rx Filter Cal */
|
||||
OS_REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
|
||||
OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
|
||||
OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
|
||||
AR_PHY_AGC_CONTROL_FLTR_CAL);
|
||||
} else if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
|
||||
/* Enable Rx Filter Cal */
|
||||
OS_REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
|
||||
OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
|
||||
@ -566,9 +618,15 @@ ar5416LoadNF(struct ath_hal *ah, const struct ieee80211_channel *chan)
|
||||
}
|
||||
|
||||
void
|
||||
ar5416InitNfHistBuff(struct ar5212NfCalHist *h)
|
||||
ar5416InitNfHistBuff(struct ath_hal *ah, struct ar5212NfCalHist *h)
|
||||
{
|
||||
int i, j;
|
||||
int16_t privNF;
|
||||
|
||||
if (AR_SREV_KITE(ah))
|
||||
privNF = AR9285_CCA_MAX_GOOD_VALUE;
|
||||
else
|
||||
privNF = AR5416_CCA_MAX_GOOD_VALUE;
|
||||
|
||||
for (i = 0; i < AR5416_NUM_NF_READINGS; i ++) {
|
||||
h[i].currIndex = 0;
|
||||
|
||||
@ -116,5 +116,5 @@ void ar5416AdcGainCalCollect(struct ath_hal *ah);
|
||||
void ar5416AdcGainCalibration(struct ath_hal *ah, uint8_t numChains);
|
||||
void ar5416AdcDcCalCollect(struct ath_hal *ah);
|
||||
void ar5416AdcDcCalibration(struct ath_hal *ah, uint8_t numChains);
|
||||
void ar5416InitNfHistBuff(struct ar5212NfCalHist *h);
|
||||
void ar5416InitNfHistBuff(struct ath_hal *ah, struct ar5212NfCalHist *h);
|
||||
#endif /* _ATH_AR5416_CAL_H_ */
|
||||
|
||||
@ -146,7 +146,9 @@ ar5416GpioGet(struct ath_hal *ah, uint32_t gpio)
|
||||
* Read output value for all gpio's, shift it,
|
||||
* and verify whether the specific bit is set.
|
||||
*/
|
||||
if (AR_SREV_MERLIN_10_OR_LATER(ah))
|
||||
if (AR_SREV_KITE_10_OR_LATER(ah))
|
||||
bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR9285_GPIO_IN_VAL);
|
||||
else if (AR_SREV_MERLIN_10_OR_LATER(ah))
|
||||
bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR928X_GPIO_IN_VAL);
|
||||
else
|
||||
bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL);
|
||||
|
||||
@ -23,6 +23,7 @@
|
||||
#include "ah_devid.h"
|
||||
|
||||
#include "ah_eeprom_v14.h"
|
||||
#include "ah_eeprom_v4k.h"
|
||||
|
||||
#include "ar5416/ar5416.h"
|
||||
#include "ar5416/ar5416reg.h"
|
||||
@ -59,15 +60,17 @@ static void ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *ch
|
||||
static HAL_BOOL ar5416SetBoardValues(struct ath_hal *, const struct ieee80211_channel *);
|
||||
static HAL_BOOL ar5416SetPowerPerRateTable(struct ath_hal *ah,
|
||||
struct ar5416eeprom *pEepData,
|
||||
struct ar5416eeprom_4k *pEepData4k,
|
||||
const struct ieee80211_channel *chan, int16_t *ratesArray,
|
||||
uint16_t cfgCtl, uint16_t AntennaReduction,
|
||||
uint16_t twiceMaxRegulatoryPower,
|
||||
uint16_t powerLimit);
|
||||
static HAL_BOOL ar5416SetPowerCalTable(struct ath_hal *ah,
|
||||
struct ar5416eeprom *pEepData,
|
||||
struct ar5416eeprom_4k *pEepData4k,
|
||||
const struct ieee80211_channel *chan,
|
||||
int16_t *pTxPowerIndexOffset);
|
||||
static uint16_t ar5416GetMaxEdgePower(uint16_t freq,
|
||||
static uint16_t ar5416GetMaxEdgePower(struct ath_hal *ah, uint16_t freq,
|
||||
CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz);
|
||||
static void ar5416GetTargetPowers(struct ath_hal *ah,
|
||||
const struct ieee80211_channel *chan, CAL_TARGET_POWER_HT *powInfo,
|
||||
@ -83,6 +86,7 @@ static int16_t interpolate(uint16_t target, uint16_t srcLeft,
|
||||
static void ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan);
|
||||
static void ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah,
|
||||
const struct ieee80211_channel *chan, CAL_DATA_PER_FREQ *pRawDataSet,
|
||||
CAL_DATA_PER_FREQ_4K *pRawDataSet4k,
|
||||
uint8_t * bChans, uint16_t availPiers,
|
||||
uint16_t tPdGainOverlap, int16_t *pMinCalPower,
|
||||
uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues,
|
||||
@ -477,7 +481,12 @@ ar5416InitDMA(struct ath_hal *ah)
|
||||
* reduce the number of usable entries in PCU TXBUF to avoid
|
||||
* wrap around.
|
||||
*/
|
||||
OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL, AR_PCU_TXBUF_CTRL_USABLE_SIZE);
|
||||
if (AR_SREV_KITE(ah))
|
||||
OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
|
||||
AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
|
||||
else
|
||||
OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
|
||||
AR_PCU_TXBUF_CTRL_USABLE_SIZE);
|
||||
}
|
||||
|
||||
static void
|
||||
@ -801,6 +810,7 @@ ar5416SetTransmitPower(struct ath_hal *ah,
|
||||
#define N(a) (sizeof (a) / sizeof (a[0]))
|
||||
|
||||
MODAL_EEP_HEADER *pModal;
|
||||
MODAL_EEP4K_HEADER *pModal4k;
|
||||
struct ath_hal_5212 *ahp = AH5212(ah);
|
||||
int16_t ratesArray[Ar5416RateSize];
|
||||
int16_t txPowerIndexOffset = 0;
|
||||
@ -812,8 +822,10 @@ ar5416SetTransmitPower(struct ath_hal *ah,
|
||||
uint16_t twiceAntennaReduction;
|
||||
uint16_t twiceMaxRegulatoryPower;
|
||||
int16_t maxPower;
|
||||
HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;
|
||||
struct ar5416eeprom *pEepData = &ee->ee_base;
|
||||
HAL_EEPROM_v14 *ee;
|
||||
HAL_EEPROM_v4k *ee4k;
|
||||
struct ar5416eeprom *pEepData;
|
||||
struct ar5416eeprom_4k *pEepData4k;
|
||||
|
||||
HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
|
||||
|
||||
@ -823,15 +835,32 @@ ar5416SetTransmitPower(struct ath_hal *ah,
|
||||
powerLimit = chan->ic_maxregpower * 2;
|
||||
twiceAntennaReduction = chan->ic_maxantgain;
|
||||
twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit);
|
||||
pModal = &pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)];
|
||||
if (AR_SREV_KITE(ah)) {
|
||||
ee4k = AH_PRIVATE(ah)->ah_eeprom;
|
||||
pEepData4k = &ee4k->ee_base;
|
||||
pModal4k = &pEepData4k->modalHeader;
|
||||
ee = NULL;
|
||||
pEepData = NULL;
|
||||
pModal = NULL;
|
||||
} else {
|
||||
ee = AH_PRIVATE(ah)->ah_eeprom;
|
||||
pEepData = &ee->ee_base;
|
||||
pModal = &pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)];
|
||||
ee4k = NULL;
|
||||
pEepData4k = NULL;
|
||||
pModal4k = NULL;
|
||||
}
|
||||
HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n",
|
||||
__func__,chan->ic_freq, cfgCtl );
|
||||
|
||||
if (IS_EEP_MINOR_V2(ah)) {
|
||||
ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
|
||||
if (pModal)
|
||||
ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
|
||||
else
|
||||
ht40PowerIncForPdadc = pModal4k->ht40PowerIncForPdadc;
|
||||
}
|
||||
|
||||
if (!ar5416SetPowerPerRateTable(ah, pEepData, chan,
|
||||
|
||||
if (!ar5416SetPowerPerRateTable(ah, pEepData, pEepData4k, chan,
|
||||
&ratesArray[0],cfgCtl,
|
||||
twiceAntennaReduction,
|
||||
twiceMaxRegulatoryPower, powerLimit)) {
|
||||
@ -840,7 +869,8 @@ ar5416SetTransmitPower(struct ath_hal *ah,
|
||||
return AH_FALSE;
|
||||
}
|
||||
|
||||
if (!ar5416SetPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) {
|
||||
if (!ar5416SetPowerCalTable(ah, pEepData, pEepData4k, chan,
|
||||
&txPowerIndexOffset)) {
|
||||
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n",
|
||||
__func__);
|
||||
return AH_FALSE;
|
||||
@ -947,10 +977,11 @@ ar5416SetTransmitPower(struct ath_hal *ah,
|
||||
}
|
||||
|
||||
/* Write the Power subtraction for dynamic chain changing, for per-packet powertx */
|
||||
OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
|
||||
POW_SM(pModal->pwrDecreaseFor3Chain, 6)
|
||||
| POW_SM(pModal->pwrDecreaseFor2Chain, 0)
|
||||
);
|
||||
if (pModal)
|
||||
OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
|
||||
POW_SM(pModal->pwrDecreaseFor3Chain, 6)
|
||||
| POW_SM(pModal->pwrDecreaseFor2Chain, 0)
|
||||
);
|
||||
return AH_TRUE;
|
||||
#undef POW_SM
|
||||
#undef N
|
||||
@ -1188,23 +1219,42 @@ ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan)
|
||||
static HAL_BOOL
|
||||
ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
|
||||
{
|
||||
const HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;
|
||||
const struct ar5416eeprom *eep = &ee->ee_base;
|
||||
const HAL_EEPROM_v14 *ee;
|
||||
const HAL_EEPROM_v4k *ee4k;
|
||||
const struct ar5416eeprom *eep;
|
||||
const struct ar5416eeprom_4k *eep4k;
|
||||
const MODAL_EEP_HEADER *pModal;
|
||||
const MODAL_EEP4K_HEADER *pModal4k;
|
||||
int i, regChainOffset;
|
||||
uint8_t txRxAttenLocal; /* workaround for eeprom versions <= 14.2 */
|
||||
|
||||
HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
|
||||
pModal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)];
|
||||
|
||||
if (AR_SREV_KITE(ah)) {
|
||||
ee4k = AH_PRIVATE(ah)->ah_eeprom;
|
||||
eep4k = &ee4k->ee_base;
|
||||
pModal4k = &eep4k->modalHeader;
|
||||
ee = NULL;
|
||||
eep = NULL;
|
||||
pModal = NULL;
|
||||
} else {
|
||||
ee = AH_PRIVATE(ah)->ah_eeprom;
|
||||
eep = &ee->ee_base;
|
||||
pModal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)];
|
||||
ee4k = NULL;
|
||||
eep4k = NULL;
|
||||
pModal4k = NULL;
|
||||
}
|
||||
|
||||
/* NB: workaround for eeprom versions <= 14.2 */
|
||||
txRxAttenLocal = IEEE80211_IS_CHAN_2GHZ(chan) ? 23 : 44;
|
||||
|
||||
OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
|
||||
OS_REG_WRITE(ah, AR_PHY_SWITCH_COM,
|
||||
(pModal) ? pModal->antCtrlCommon :
|
||||
pModal4k->antCtrlCommon);
|
||||
for (i = 0; i < AR5416_MAX_CHAINS; i++) {
|
||||
if (AR_SREV_MERLIN(ah)) {
|
||||
if (i >= 2) break;
|
||||
}
|
||||
if (AR_SREV_KITE(ah) && i >= 1) break;
|
||||
if (AR_SREV_MERLIN(ah) && i >= 2) break;
|
||||
if (AR_SREV_OWL_20_OR_LATER(ah) &&
|
||||
(AH5416(ah)->ah_rx_chainmask == 0x5 ||
|
||||
AH5416(ah)->ah_tx_chainmask == 0x5) && i != 0) {
|
||||
@ -1216,12 +1266,15 @@ ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
|
||||
regChainOffset = i * 0x1000;
|
||||
}
|
||||
|
||||
OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, pModal->antCtrlChain[i]);
|
||||
OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
|
||||
(pModal) ? pModal->antCtrlChain[i] : pModal4k->antCtrlChain[i]);
|
||||
OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset,
|
||||
(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) &
|
||||
~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
|
||||
SM(pModal->iqCalICh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
|
||||
SM(pModal->iqCalQCh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
|
||||
SM((pModal) ? pModal->iqCalICh[i] : pModal4k->iqCalICh[i],
|
||||
AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
|
||||
SM((pModal) ? pModal->iqCalQCh[i] : pModal4k->iqCalQCh[i],
|
||||
AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
|
||||
|
||||
/*
|
||||
* Large signal upgrade.
|
||||
@ -1229,54 +1282,74 @@ ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
|
||||
*/
|
||||
|
||||
if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) {
|
||||
int txRxAtten;
|
||||
if (IS_EEP_MINOR_V3(ah)) {
|
||||
if (pModal) txRxAtten = pModal->txRxAttenCh[i];
|
||||
else txRxAtten = pModal4k->txRxAttenCh[i];
|
||||
} else
|
||||
txRxAtten = txRxAttenLocal;
|
||||
|
||||
OS_REG_WRITE(ah, AR_PHY_RXGAIN + regChainOffset,
|
||||
(OS_REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) & ~AR_PHY_RXGAIN_TXRX_ATTEN) |
|
||||
SM(IS_EEP_MINOR_V3(ah) ? pModal->txRxAttenCh[i] : txRxAttenLocal,
|
||||
AR_PHY_RXGAIN_TXRX_ATTEN));
|
||||
SM(txRxAtten, AR_PHY_RXGAIN_TXRX_ATTEN));
|
||||
|
||||
OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
|
||||
(OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
|
||||
SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
|
||||
SM((pModal) ? pModal->rxTxMarginCh[i]:
|
||||
pModal4k->rxTxMarginCh[i],
|
||||
AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
|
||||
}
|
||||
}
|
||||
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->switchSettling);
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA, pModal->pgaDesiredSize);
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
|
||||
(pModal) ? pModal->switchSettling : pModal4k->switchSettling);
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
|
||||
(pModal) ? pModal->adcDesiredSize : pModal4k->adcDesiredSize);
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA,
|
||||
(pModal) ? pModal->pgaDesiredSize : pModal4k->pgaDesiredSize);
|
||||
OS_REG_WRITE(ah, AR_PHY_RF_CTL4,
|
||||
SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
|
||||
| SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
|
||||
| SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)
|
||||
| SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
|
||||
SM((pModal) ? pModal->txEndToXpaOff : pModal4k->txEndToXpaOff,
|
||||
AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
|
||||
| SM((pModal) ? pModal->txEndToXpaOff : pModal4k->txEndToXpaOff,
|
||||
AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
|
||||
| SM((pModal) ? pModal->txFrameToXpaOn : pModal4k->txFrameToXpaOn,
|
||||
AR_PHY_RF_CTL4_FRAME_XPAA_ON)
|
||||
| SM((pModal) ? pModal->txFrameToXpaOn : pModal4k->txFrameToXpaOn,
|
||||
AR_PHY_RF_CTL4_FRAME_XPAB_ON));
|
||||
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn);
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
|
||||
(pModal) ? pModal->txEndToRxOn : pModal4k->txEndToRxOn);
|
||||
|
||||
if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
|
||||
pModal->thresh62);
|
||||
(pModal) ? pModal->thresh62 : pModal4k->thresh62);
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
|
||||
pModal->thresh62);
|
||||
(pModal) ? pModal->thresh62 : pModal4k->thresh62);
|
||||
} else {
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
|
||||
pModal->thresh62);
|
||||
(pModal) ? pModal->thresh62 : pModal4k->thresh62);
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA_THRESH62,
|
||||
pModal->thresh62);
|
||||
(pModal) ? pModal->thresh62 : pModal4k->thresh62);
|
||||
}
|
||||
|
||||
/* Minor Version Specific application */
|
||||
if (IS_EEP_MINOR_V2(ah)) {
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START, pModal->txFrameToDataStart);
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON, pModal->txFrameToPaOn);
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START,
|
||||
(pModal) ? pModal->txFrameToDataStart : pModal4k->txFrameToDataStart);
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON,
|
||||
(pModal) ? pModal->txFrameToPaOn : pModal4k->txFrameToPaOn);
|
||||
}
|
||||
|
||||
if (IS_EEP_MINOR_V3(ah)) {
|
||||
if (IEEE80211_IS_CHAN_HT40(chan)) {
|
||||
/* Overwrite switch settling with HT40 value */
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
|
||||
(pModal) ? pModal->swSettleHt40 : pModal4k->swSettleHt40);
|
||||
}
|
||||
|
||||
if ((AR_SREV_OWL_20_OR_LATER(ah)) &&
|
||||
( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5)){
|
||||
/* NB: no v4k EEPROM */
|
||||
/* Reg Offsets are swapped for logical mapping */
|
||||
OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
|
||||
SM(pModal->bswMargin[2], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
|
||||
@ -1288,16 +1361,22 @@ ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
|
||||
SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
|
||||
} else {
|
||||
OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
|
||||
SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
|
||||
SM((pModal) ? pModal->bswMargin[1] :
|
||||
pModal4k->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
|
||||
OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
|
||||
SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
|
||||
SM((pModal) ? pModal->bswAtten[1] :
|
||||
pModal4k->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
|
||||
OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
|
||||
SM(pModal->bswMargin[2],AR_PHY_GAIN_2GHZ_BSW_MARGIN));
|
||||
SM((pModal) ? pModal->bswMargin[2] :
|
||||
pModal4k->bswMargin[2], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
|
||||
OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
|
||||
SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
|
||||
SM((pModal) ? pModal->bswAtten[2] :
|
||||
pModal4k->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
|
||||
}
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_MARGIN, pModal->bswMargin[0]);
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_ATTEN, pModal->bswAtten[0]);
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_MARGIN,
|
||||
(pModal) ? pModal->bswMargin[0] : pModal4k->bswMargin[0]);
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_ATTEN,
|
||||
(pModal) ? pModal->bswAtten[0] : pModal4k->bswAtten[0]);
|
||||
}
|
||||
return AH_TRUE;
|
||||
}
|
||||
@ -1312,8 +1391,9 @@ ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
|
||||
* Sets the transmit power in the baseband for the given
|
||||
* operating channel and mode.
|
||||
*/
|
||||
static HAL_BOOL
|
||||
HAL_BOOL
|
||||
ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
|
||||
struct ar5416eeprom_4k *pEepData4k,
|
||||
const struct ieee80211_channel *chan,
|
||||
int16_t *ratesArray, uint16_t cfgCtl,
|
||||
uint16_t AntennaReduction,
|
||||
@ -1331,6 +1411,7 @@ ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
|
||||
int i;
|
||||
int16_t twiceLargestAntenna;
|
||||
CAL_CTL_DATA *rep;
|
||||
CAL_CTL_DATA_4K *rep4k;
|
||||
CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}};
|
||||
CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}};
|
||||
CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}};
|
||||
@ -1347,15 +1428,22 @@ ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
|
||||
const uint16_t *pCtlMode;
|
||||
uint16_t numCtlModes, ctlMode, freq;
|
||||
CHAN_CENTERS centers;
|
||||
int n2gcck, n2g20, n2g40, numctls;
|
||||
|
||||
ar5416GetChannelCenters(ah, chan, ¢ers);
|
||||
|
||||
/* Compute TxPower reduction due to Antenna Gain */
|
||||
|
||||
twiceLargestAntenna = AH_MAX(AH_MAX(
|
||||
pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[0],
|
||||
pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[1]),
|
||||
pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
|
||||
if (pEepData)
|
||||
twiceLargestAntenna = AH_MAX(AH_MAX(
|
||||
pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[0],
|
||||
pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[1]),
|
||||
pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
|
||||
else
|
||||
twiceLargestAntenna = AH_MAX(AH_MAX(
|
||||
pEepData4k->modalHeader.antennaGainCh[0],
|
||||
pEepData4k->modalHeader.antennaGainCh[1]),
|
||||
pEepData4k->modalHeader.antennaGainCh[2]);
|
||||
#if 0
|
||||
/* Turn it back on if we need to calculate per chain antenna gain reduction */
|
||||
/* Use only if the expected gain > 6dbi */
|
||||
@ -1390,10 +1478,12 @@ ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
|
||||
case 1:
|
||||
break;
|
||||
case 2:
|
||||
scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor2Chain;
|
||||
if (pEepData)
|
||||
scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor2Chain;
|
||||
break;
|
||||
case 3:
|
||||
scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor3Chain;
|
||||
if (pEepData)
|
||||
scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor3Chain;
|
||||
break;
|
||||
default:
|
||||
return AH_FALSE; /* Unsupported number of chains */
|
||||
@ -1401,36 +1491,56 @@ ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
|
||||
|
||||
scaledPower = AH_MAX(0, scaledPower);
|
||||
|
||||
n2gcck = (pEepData) ? AR5416_NUM_2G_CCK_TARGET_POWERS :
|
||||
AR5416_4K_NUM_2G_CCK_TARGET_POWERS;
|
||||
n2g20 = (pEepData) ? AR5416_NUM_2G_20_TARGET_POWERS :
|
||||
AR5416_4K_NUM_2G_20_TARGET_POWERS;
|
||||
n2g40 = (pEepData) ? AR5416_NUM_2G_40_TARGET_POWERS :
|
||||
AR5416_4K_NUM_2G_40_TARGET_POWERS;
|
||||
|
||||
/* Get target powers from EEPROM - our baseline for TX Power */
|
||||
if (IEEE80211_IS_CHAN_2GHZ(chan)) {
|
||||
/* Setup for CTL modes */
|
||||
numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */
|
||||
pCtlMode = ctlModesFor11g;
|
||||
|
||||
ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck,
|
||||
AR5416_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE);
|
||||
ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G,
|
||||
AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE);
|
||||
ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20,
|
||||
AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE);
|
||||
ar5416GetTargetPowersLeg(ah, chan,
|
||||
(pEepData) ? pEepData->calTargetPowerCck :
|
||||
pEepData4k->calTargetPowerCck,
|
||||
n2gcck, &targetPowerCck, 4, AH_FALSE);
|
||||
ar5416GetTargetPowersLeg(ah, chan,
|
||||
(pEepData) ? pEepData->calTargetPower2G :
|
||||
pEepData4k->calTargetPower2G,
|
||||
n2g20, &targetPowerOfdm, 4, AH_FALSE);
|
||||
ar5416GetTargetPowers(ah, chan,
|
||||
(pEepData) ? pEepData->calTargetPower2GHT20 :
|
||||
pEepData4k->calTargetPower2GHT20,
|
||||
n2g20, &targetPowerHt20, 8, AH_FALSE);
|
||||
|
||||
if (IEEE80211_IS_CHAN_HT40(chan)) {
|
||||
numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */
|
||||
|
||||
ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40,
|
||||
AR5416_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE);
|
||||
ar5416GetTargetPowers(ah, chan,
|
||||
(pEepData) ? pEepData->calTargetPower2GHT40 :
|
||||
pEepData4k->calTargetPower2GHT40,
|
||||
n2g40, &targetPowerHt40, 8, AH_TRUE);
|
||||
/* Get target powers for extension channels */
|
||||
ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck,
|
||||
AR5416_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE);
|
||||
ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G,
|
||||
AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE);
|
||||
ar5416GetTargetPowersLeg(ah, chan,
|
||||
(pEepData) ? pEepData->calTargetPowerCck :
|
||||
pEepData4k->calTargetPowerCck,
|
||||
n2gcck, &targetPowerCckExt, 4, AH_TRUE);
|
||||
ar5416GetTargetPowersLeg(ah, chan,
|
||||
(pEepData) ? pEepData->calTargetPower2G :
|
||||
pEepData4k->calTargetPower2G,
|
||||
n2g20, &targetPowerOfdmExt, 4, AH_TRUE);
|
||||
}
|
||||
} else {
|
||||
/* Setup for CTL modes */
|
||||
numCtlModes = N(ctlModesFor11a) - SUB_NUM_CTL_MODES_AT_5G_40; /* CTL_11A, CTL_5GHT20 */
|
||||
pCtlMode = ctlModesFor11a;
|
||||
|
||||
ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G,
|
||||
/* NB: v4k EEPROM has no 5Ghz info */
|
||||
ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G,
|
||||
AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE);
|
||||
ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT20,
|
||||
AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE);
|
||||
@ -1454,7 +1564,9 @@ ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
|
||||
* The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
|
||||
*
|
||||
*/
|
||||
numctls = (pEepData) ? AR5416_NUM_CTLS : AR5416_4K_NUM_CTLS;
|
||||
for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
|
||||
int ctlIndex;
|
||||
HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
|
||||
(pCtlMode[ctlMode] == CTL_2GHT40);
|
||||
if (isHt40CtlMode) {
|
||||
@ -1465,18 +1577,34 @@ ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
|
||||
freq = centers.ctl_center;
|
||||
}
|
||||
|
||||
ctlIndex = (pEepData) ? pEepData->ctlIndex[0] :
|
||||
pEepData4k->ctlIndex[0];
|
||||
/* walk through each CTL index stored in EEPROM */
|
||||
for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
|
||||
for (i = 0; (i < numctls) && ctlIndex; i++) {
|
||||
uint16_t twiceMinEdgePower;
|
||||
CAL_CTL_EDGES *ctlEdge;
|
||||
|
||||
ctlIndex = (pEepData) ? pEepData->ctlIndex[i] :
|
||||
pEepData4k->ctlIndex[i];
|
||||
|
||||
/* compare test group from regulatory channel list with test mode from pCtlMode list */
|
||||
if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) ||
|
||||
if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == ctlIndex) ||
|
||||
(((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) ==
|
||||
((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
|
||||
rep = &(pEepData->ctlData[i]);
|
||||
twiceMinEdgePower = ar5416GetMaxEdgePower(freq,
|
||||
rep->ctlEdges[owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1],
|
||||
IEEE80211_IS_CHAN_2GHZ(chan));
|
||||
((ctlIndex & CTL_MODE_M) | SD_NO_CTL))) {
|
||||
if (pEepData) {
|
||||
rep = &(pEepData->ctlData[i]);
|
||||
ctlEdge = rep->ctlEdges[
|
||||
owl_get_ntxchains(
|
||||
AH5416(ah)->ah_tx_chainmask) - 1];
|
||||
} else {
|
||||
rep4k = &(pEepData4k->ctlData[i]);
|
||||
ctlEdge = rep4k->ctlEdges[
|
||||
owl_get_ntxchains(
|
||||
AH5416(ah)->ah_tx_chainmask) - 1];
|
||||
}
|
||||
twiceMinEdgePower = ar5416GetMaxEdgePower(ah,
|
||||
freq, ctlEdge,
|
||||
IEEE80211_IS_CHAN_2GHZ(chan));
|
||||
if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
|
||||
/* Find the minimum of all CTL edge powers that apply to this channel */
|
||||
twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower);
|
||||
@ -1590,13 +1718,19 @@ fbin2freq(uint8_t fbin, HAL_BOOL is2GHz)
|
||||
* Find the maximum conformance test limit for the given channel and CTL info
|
||||
*/
|
||||
static uint16_t
|
||||
ar5416GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz)
|
||||
ar5416GetMaxEdgePower(struct ath_hal *ah,
|
||||
uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz)
|
||||
{
|
||||
uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
|
||||
int i;
|
||||
int i, numBand;
|
||||
|
||||
if (AR_SREV_KITE(ah))
|
||||
numBand = AR5416_4K_NUM_BAND_EDGES;
|
||||
else
|
||||
numBand = AR5416_NUM_BAND_EDGES;
|
||||
|
||||
/* Get the edge power */
|
||||
for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) {
|
||||
for (i = 0; (i < numBand) && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) {
|
||||
/*
|
||||
* If there's an exact channel match or an inband flag set
|
||||
* on the lower channel use the given rdEdgePower
|
||||
@ -1743,11 +1877,13 @@ ar5416GetTargetPowersLeg(struct ath_hal *ah,
|
||||
* points as well as from the nearest pier(s) to get a power detector
|
||||
* linear voltage to power level table.
|
||||
*/
|
||||
static HAL_BOOL
|
||||
HAL_BOOL
|
||||
ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
|
||||
struct ar5416eeprom_4k *pEepData4k,
|
||||
const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset)
|
||||
{
|
||||
CAL_DATA_PER_FREQ *pRawDataset;
|
||||
CAL_DATA_PER_FREQ *pRawDataset = NULL;
|
||||
CAL_DATA_PER_FREQ_4K *pRawDataset4k = NULL;
|
||||
uint8_t *pCalBChans = AH_NULL;
|
||||
uint16_t pdGainOverlap_t2;
|
||||
static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES];
|
||||
@ -1760,17 +1896,28 @@ ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
|
||||
|
||||
OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues));
|
||||
|
||||
xpdMask = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].xpdGain;
|
||||
if (pEepData)
|
||||
xpdMask = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].xpdGain;
|
||||
else
|
||||
xpdMask = pEepData4k->modalHeader.xpdGain;
|
||||
|
||||
if (IS_EEP_MINOR_V2(ah)) {
|
||||
pdGainOverlap_t2 = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pdGainOverlap;
|
||||
if (pEepData)
|
||||
pdGainOverlap_t2 = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pdGainOverlap;
|
||||
else
|
||||
pdGainOverlap_t2 = pEepData4k->modalHeader.pdGainOverlap;
|
||||
} else {
|
||||
pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
|
||||
}
|
||||
|
||||
if (IEEE80211_IS_CHAN_2GHZ(chan)) {
|
||||
pCalBChans = pEepData->calFreqPier2G;
|
||||
numPiers = AR5416_NUM_2G_CAL_PIERS;
|
||||
if (pEepData) {
|
||||
pCalBChans = pEepData->calFreqPier2G;
|
||||
numPiers = AR5416_NUM_2G_CAL_PIERS;
|
||||
} else {
|
||||
pCalBChans = pEepData4k->calFreqPier2G;
|
||||
numPiers = AR5416_4K_NUM_2G_CAL_PIERS;
|
||||
}
|
||||
} else {
|
||||
pCalBChans = pEepData->calFreqPier5G;
|
||||
numPiers = AR5416_NUM_5G_CAL_PIERS;
|
||||
@ -1796,7 +1943,7 @@ ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
|
||||
SM(xpdGainValues[1], AR_PHY_TPCRG1_PD_GAIN_2) | SM(xpdGainValues[2], AR_PHY_TPCRG1_PD_GAIN_3));
|
||||
|
||||
for (i = 0; i < AR5416_MAX_CHAINS; i++) {
|
||||
|
||||
if (AR_SREV_KITE(ah) && i >= AR5416_4K_MAX_CHAINS) break;
|
||||
if (AR_SREV_OWL_20_OR_LATER(ah) &&
|
||||
( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5) && (i != 0)) {
|
||||
/* Regs are swapped from chain 2 to 1 for 5416 2_0 with
|
||||
@ -1807,14 +1954,22 @@ ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
|
||||
regChainOffset = i * 0x1000;
|
||||
}
|
||||
|
||||
if (pEepData->baseEepHeader.txMask & (1 << i)) {
|
||||
int txMask;
|
||||
txMask = (pEepData) ? pEepData->baseEepHeader.txMask :
|
||||
pEepData4k->baseEepHeader.txMask;
|
||||
|
||||
if (txMask & (1 << i)) {
|
||||
if (IEEE80211_IS_CHAN_2GHZ(chan)) {
|
||||
pRawDataset = pEepData->calPierData2G[i];
|
||||
if (pEepData)
|
||||
pRawDataset = pEepData->calPierData2G[i];
|
||||
else
|
||||
pRawDataset4k = pEepData4k->calPierData2G[i];
|
||||
} else {
|
||||
pRawDataset = pEepData->calPierData5G[i];
|
||||
}
|
||||
|
||||
ar5416GetGainBoundariesAndPdadcs(ah, chan, pRawDataset,
|
||||
ar5416GetGainBoundariesAndPdadcs(ah, chan, pRawDataset,
|
||||
pRawDataset4k,
|
||||
pCalBChans, numPiers,
|
||||
pdGainOverlap_t2,
|
||||
&tMinCalPower, gainBoundaries,
|
||||
@ -1872,8 +2027,10 @@ static void
|
||||
ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah,
|
||||
const struct ieee80211_channel *chan,
|
||||
CAL_DATA_PER_FREQ *pRawDataSet,
|
||||
CAL_DATA_PER_FREQ_4K *pRawDataSet4k,
|
||||
uint8_t * bChans, uint16_t availPiers,
|
||||
uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries,
|
||||
uint16_t tPdGainOverlap, int16_t *pMinCalPower,
|
||||
uint16_t * pPdGainBoundaries,
|
||||
uint8_t * pPDADCValues, uint16_t numXpdGains)
|
||||
{
|
||||
|
||||
@ -1916,17 +2073,35 @@ ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah,
|
||||
if (match) {
|
||||
/* Directly fill both vpd tables from the matching index */
|
||||
for (i = 0; i < numXpdGains; i++) {
|
||||
minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
|
||||
maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
|
||||
ar5416FillVpdTable(minPwrT4[i], maxPwrT4[i], pRawDataSet[idxL].pwrPdg[i],
|
||||
pRawDataSet[idxL].vpdPdg[i], AR5416_PD_GAIN_ICEPTS, vpdTableI[i]);
|
||||
if (pRawDataSet) {
|
||||
minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
|
||||
maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
|
||||
ar5416FillVpdTable(minPwrT4[i], maxPwrT4[i],
|
||||
pRawDataSet[idxL].pwrPdg[i],
|
||||
pRawDataSet[idxL].vpdPdg[i],
|
||||
AR5416_PD_GAIN_ICEPTS, vpdTableI[i]);
|
||||
} else {
|
||||
minPwrT4[i] = pRawDataSet4k[idxL].pwrPdg[i][0];
|
||||
maxPwrT4[i] = pRawDataSet4k[idxL].pwrPdg[i][4];
|
||||
ar5416FillVpdTable(minPwrT4[i], maxPwrT4[i],
|
||||
pRawDataSet4k[idxL].pwrPdg[i],
|
||||
pRawDataSet4k[idxL].vpdPdg[i],
|
||||
AR5416_PD_GAIN_ICEPTS, vpdTableI[i]);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
for (i = 0; i < numXpdGains; i++) {
|
||||
pVpdL = pRawDataSet[idxL].vpdPdg[i];
|
||||
pPwrL = pRawDataSet[idxL].pwrPdg[i];
|
||||
pVpdR = pRawDataSet[idxR].vpdPdg[i];
|
||||
pPwrR = pRawDataSet[idxR].pwrPdg[i];
|
||||
if (pRawDataSet) {
|
||||
pVpdL = pRawDataSet[idxL].vpdPdg[i];
|
||||
pPwrL = pRawDataSet[idxL].pwrPdg[i];
|
||||
pVpdR = pRawDataSet[idxR].vpdPdg[i];
|
||||
pPwrR = pRawDataSet[idxR].pwrPdg[i];
|
||||
} else {
|
||||
pVpdL = pRawDataSet4k[idxL].vpdPdg[i];
|
||||
pPwrL = pRawDataSet4k[idxL].pwrPdg[i];
|
||||
pVpdR = pRawDataSet4k[idxR].vpdPdg[i];
|
||||
pPwrR = pRawDataSet4k[idxR].pwrPdg[i];
|
||||
}
|
||||
|
||||
/* Start Vpd interpolation from the max of the minimum powers */
|
||||
minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]);
|
||||
|
||||
@ -14,7 +14,7 @@
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $Id: ar5416phy.h,v 1.10 2008/11/11 20:46:06 sam Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#ifndef _DEV_ATH_AR5416PHY_H_
|
||||
#define _DEV_ATH_AR5416PHY_H_
|
||||
@ -207,6 +207,9 @@
|
||||
#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
|
||||
#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
|
||||
|
||||
#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
|
||||
#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
|
||||
|
||||
#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
|
||||
#define AR_PHY_MASK2_M_31_45 0xa3a4
|
||||
#define AR_PHY_MASK2_M_16_30 0xa3a8
|
||||
@ -247,4 +250,5 @@
|
||||
|
||||
#define AR_PHY_CL_CAL_CTL 0xA358 /* carrier leak cal control */
|
||||
#define AR_PHY_CL_CAL_ENABLE 0x00000002
|
||||
#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
|
||||
#endif /* _DEV_ATH_AR5416PHY_H_ */
|
||||
|
||||
@ -70,8 +70,20 @@
|
||||
#define AR_AN_RF5G1_CH1 0x783C
|
||||
#define AR_AN_TOP2 0x7894
|
||||
#define AR_AN_SYNTH9 0x7868
|
||||
#define AR9285_AN_RF2G3 0x7828
|
||||
#define AR9285_AN_RF2G1 0x7820
|
||||
#define AR9285_AN_RF2G2 0x7824
|
||||
#define AR9285_AN_RF2G3 0x7828
|
||||
#define AR9285_AN_RF2G4 0x782C
|
||||
#define AR9285_AN_RF2G6 0x7834
|
||||
#define AR9285_AN_RF2G7 0x7838
|
||||
#define AR9285_AN_RF2G8 0x783C
|
||||
#define AR9285_AN_RF2G9 0x7840
|
||||
#define AR9285_AN_RXTXBB1 0x7854
|
||||
#define AR9285_AN_TOP2 0x7868
|
||||
#define AR9285_AN_TOP3 0x786c
|
||||
#define AR9285_AN_TOP4 0x7870
|
||||
#define AR9285_AN_TOP4_DEFAULT 0x10142c00
|
||||
|
||||
#define AR_RESET_TSF 0x8020
|
||||
#define AR_RXFIFO_CFG 0x8114
|
||||
#define AR_PHY_ERR_1 0x812c
|
||||
@ -359,42 +371,83 @@
|
||||
#define AR_AN_SYNTH9_REFDIVA_S 27
|
||||
|
||||
/* AR9285 Analog registers */
|
||||
#define AR9285_AN_RF2G3_OB_0 0x00E00000
|
||||
#define AR9285_AN_RF2G3_OB_0_S 21
|
||||
#define AR9285_AN_RF2G3_OB_1 0x001C0000
|
||||
#define AR9285_AN_RF2G3_OB_1_S 18
|
||||
#define AR9285_AN_RF2G3_OB_2 0x00038000
|
||||
#define AR9285_AN_RF2G3_OB_2_S 15
|
||||
#define AR9285_AN_RF2G3_OB_3 0x00007000
|
||||
#define AR9285_AN_RF2G3_OB_3_S 12
|
||||
#define AR9285_AN_RF2G3_OB_4 0x00000E00
|
||||
#define AR9285_AN_RF2G3_OB_4_S 9
|
||||
#define AR9285_AN_RF2G1_ENPACAL 0x00000800
|
||||
#define AR9285_AN_RF2G1_ENPACAL_S 11
|
||||
#define AR9285_AN_RF2G1_PDPADRV1 0x02000000
|
||||
#define AR9285_AN_RF2G1_PDPADRV1_S 25
|
||||
#define AR9285_AN_RF2G1_PDPADRV2 0x01000000
|
||||
#define AR9285_AN_RF2G1_PDPADRV2_S 24
|
||||
#define AR9285_AN_RF2G1_PDPAOUT 0x00800000
|
||||
#define AR9285_AN_RF2G1_PDPAOUT_S 23
|
||||
|
||||
#define AR9285_AN_RF2G3_DB1_0 0x000001C0
|
||||
#define AR9285_AN_RF2G3_DB1_0_S 6
|
||||
#define AR9285_AN_RF2G3_DB1_1 0x00000038
|
||||
#define AR9285_AN_RF2G3_DB1_1_S 3
|
||||
#define AR9285_AN_RF2G3_DB1_2 0x00000007
|
||||
#define AR9285_AN_RF2G3_DB1_2_S 0
|
||||
#define AR9285_AN_RF2G4 0x782C
|
||||
#define AR9285_AN_RF2G4_DB1_3 0xE0000000
|
||||
#define AR9285_AN_RF2G4_DB1_3_S 29
|
||||
#define AR9285_AN_RF2G4_DB1_4 0x1C000000
|
||||
#define AR9285_AN_RF2G4_DB1_4_S 26
|
||||
#define AR9285_AN_RF2G2_OFFCAL 0x00001000
|
||||
#define AR9285_AN_RF2G2_OFFCAL_S 12
|
||||
|
||||
#define AR9285_AN_RF2G4_DB2_0 0x03800000
|
||||
#define AR9285_AN_RF2G4_DB2_0_S 23
|
||||
#define AR9285_AN_RF2G4_DB2_1 0x00700000
|
||||
#define AR9285_AN_RF2G4_DB2_1_S 20
|
||||
#define AR9285_AN_RF2G4_DB2_2 0x000E0000
|
||||
#define AR9285_AN_RF2G4_DB2_2_S 17
|
||||
#define AR9285_AN_RF2G4_DB2_3 0x0001C000
|
||||
#define AR9285_AN_RF2G4_DB2_3_S 14
|
||||
#define AR9285_AN_RF2G4_DB2_4 0x00003800
|
||||
#define AR9285_AN_RF2G4_DB2_4_S 11
|
||||
#define AR9285_AN_RF2G3_PDVCCOMP 0x02000000
|
||||
#define AR9285_AN_RF2G3_PDVCCOMP_S 25
|
||||
#define AR9285_AN_RF2G3_OB_0 0x00E00000
|
||||
#define AR9285_AN_RF2G3_OB_0_S 21
|
||||
#define AR9285_AN_RF2G3_OB_1 0x001C0000
|
||||
#define AR9285_AN_RF2G3_OB_1_S 18
|
||||
#define AR9285_AN_RF2G3_OB_2 0x00038000
|
||||
#define AR9285_AN_RF2G3_OB_2_S 15
|
||||
#define AR9285_AN_RF2G3_OB_3 0x00007000
|
||||
#define AR9285_AN_RF2G3_OB_3_S 12
|
||||
#define AR9285_AN_RF2G3_OB_4 0x00000E00
|
||||
#define AR9285_AN_RF2G3_OB_4_S 9
|
||||
|
||||
#define AR9285_AN_RF2G3_DB1_0 0x000001C0
|
||||
#define AR9285_AN_RF2G3_DB1_0_S 6
|
||||
#define AR9285_AN_RF2G3_DB1_1 0x00000038
|
||||
#define AR9285_AN_RF2G3_DB1_1_S 3
|
||||
#define AR9285_AN_RF2G3_DB1_2 0x00000007
|
||||
#define AR9285_AN_RF2G3_DB1_2_S 0
|
||||
|
||||
#define AR9285_AN_RF2G4_DB1_3 0xE0000000
|
||||
#define AR9285_AN_RF2G4_DB1_3_S 29
|
||||
#define AR9285_AN_RF2G4_DB1_4 0x1C000000
|
||||
#define AR9285_AN_RF2G4_DB1_4_S 26
|
||||
|
||||
#define AR9285_AN_RF2G4_DB2_0 0x03800000
|
||||
#define AR9285_AN_RF2G4_DB2_0_S 23
|
||||
#define AR9285_AN_RF2G4_DB2_1 0x00700000
|
||||
#define AR9285_AN_RF2G4_DB2_1_S 20
|
||||
#define AR9285_AN_RF2G4_DB2_2 0x000E0000
|
||||
#define AR9285_AN_RF2G4_DB2_2_S 17
|
||||
#define AR9285_AN_RF2G4_DB2_3 0x0001C000
|
||||
#define AR9285_AN_RF2G4_DB2_3_S 14
|
||||
#define AR9285_AN_RF2G4_DB2_4 0x00003800
|
||||
#define AR9285_AN_RF2G4_DB2_4_S 11
|
||||
|
||||
#define AR9285_AN_RF2G6_CCOMP 0x00007800
|
||||
#define AR9285_AN_RF2G6_CCOMP_S 11
|
||||
#define AR9285_AN_RF2G6_OFFS 0x03f00000
|
||||
#define AR9285_AN_RF2G6_OFFS_S 20
|
||||
|
||||
#define AR9271_AN_RF2G6_OFFS 0x07f00000
|
||||
#define AR9271_AN_RF2G6_OFFS_S 20
|
||||
|
||||
#define AR9285_AN_RF2G7_PWDDB 0x00000002
|
||||
#define AR9285_AN_RF2G7_PWDDB_S 1
|
||||
#define AR9285_AN_RF2G7_PADRVGN2TAB0 0xE0000000
|
||||
#define AR9285_AN_RF2G7_PADRVGN2TAB0_S 29
|
||||
|
||||
#define AR9285_AN_RF2G8_PADRVGN2TAB0 0x0001C000
|
||||
#define AR9285_AN_RF2G8_PADRVGN2TAB0_S 14
|
||||
|
||||
#define AR9285_AN_RXTXBB1_PDRXTXBB1 0x00000020
|
||||
#define AR9285_AN_RXTXBB1_PDRXTXBB1_S 5
|
||||
#define AR9285_AN_RXTXBB1_PDV2I 0x00000080
|
||||
#define AR9285_AN_RXTXBB1_PDV2I_S 7
|
||||
#define AR9285_AN_RXTXBB1_PDDACIF 0x00000100
|
||||
#define AR9285_AN_RXTXBB1_PDDACIF_S 8
|
||||
#define AR9285_AN_RXTXBB1_SPARE9 0x00000001
|
||||
#define AR9285_AN_RXTXBB1_SPARE9_S 0
|
||||
|
||||
#define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C
|
||||
#define AR9285_AN_TOP3_XPABIAS_LVL_S 2
|
||||
#define AR9285_AN_TOP3_PWDDAC 0x00800000
|
||||
#define AR9285_AN_TOP3_PWDDAC_S 23
|
||||
|
||||
/* Sleep control */
|
||||
#define AR5416_SLEEP1_CAB_TIMEOUT 0xFFE00000 /* Cab timeout (TU) */
|
||||
@ -472,6 +525,7 @@
|
||||
|
||||
#define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF
|
||||
#define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700
|
||||
#define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380
|
||||
|
||||
/* Eeprom defines */
|
||||
#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff
|
||||
@ -522,6 +576,8 @@
|
||||
#define AR_XSREV_REVISION_MERLIN_21 2 /* Merlin 2.1 */
|
||||
#define AR_XSREV_VERSION_KITE 0xC0 /* Kite Version */
|
||||
#define AR_XSREV_REVISION_KITE_10 0 /* Kite 1.0 */
|
||||
#define AR_XSREV_REVISION_KITE_11 1 /* Kite 1.1 */
|
||||
#define AR_XSREV_REVISION_KITE_12 2 /* Kite 1.2 */
|
||||
|
||||
#define AR_SREV_OWL_20_OR_LATER(_ah) \
|
||||
(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL || \
|
||||
@ -553,4 +609,16 @@
|
||||
(AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KITE)
|
||||
#define AR_SREV_KITE_10_OR_LATER(_ah) \
|
||||
(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KITE)
|
||||
#define AR_SREV_KITE_11(_ah) \
|
||||
(AR_SREV_KITE(ah) && \
|
||||
AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_11)
|
||||
#define AR_SREV_KITE_11_OR_LATER(_ah) \
|
||||
(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KITE || \
|
||||
AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_11)
|
||||
#define AR_SREV_KITE_12(_ah) \
|
||||
(AR_SREV_KITE(ah) && \
|
||||
AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_12)
|
||||
#define AR_SREV_KITE_12_OR_LATER(_ah) \
|
||||
(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KITE || \
|
||||
AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_12)
|
||||
#endif /* _DEV_ATH_AR5416REG_H */
|
||||
|
||||
@ -249,7 +249,7 @@ ar9160Attach(uint16_t devid, HAL_SOFTC sc,
|
||||
OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
|
||||
|
||||
ar9160AniSetup(ah); /* Anti Noise Immunity */
|
||||
ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
|
||||
ar5416InitNfHistBuff(ah, AH5416(ah)->ah_cal.nfCalHist);
|
||||
|
||||
HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
|
||||
|
||||
|
||||
@ -23,6 +23,7 @@
|
||||
#include "ah_devid.h"
|
||||
|
||||
#include "ah_eeprom_v14.h" /* XXX for tx/rx gain */
|
||||
#include "ah_eeprom_v4k.h"
|
||||
|
||||
#include "ar5416/ar9280.h"
|
||||
#include "ar5416/ar5416reg.h"
|
||||
@ -30,6 +31,9 @@
|
||||
|
||||
#include "ar5416/ar9280v1.ini"
|
||||
#include "ar5416/ar9280v2.ini"
|
||||
#include "ar5416/ar9285.ini"
|
||||
#include "ar5416/ar9285v2.ini"
|
||||
|
||||
|
||||
static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */
|
||||
.calName = "IQ", .calType = IQ_MISMATCH_CAL,
|
||||
@ -147,7 +151,18 @@ ar9280Attach(uint16_t devid, HAL_SOFTC sc,
|
||||
AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
|
||||
|
||||
/* setup common ini data; rf backends handle remainder */
|
||||
if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
|
||||
/* XXX power consumption higer if clkreq is on */
|
||||
if (AR_SREV_KITE_12_OR_LATER(ah)) {
|
||||
HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes_v2, 6);
|
||||
HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common_v2, 2);
|
||||
HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
|
||||
ar9285PciePhy_clkreq_always_on_L1_v2, 2);
|
||||
} else if (AR_SREV_KITE_10_OR_LATER(ah)) {
|
||||
HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes, 6);
|
||||
HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common, 2);
|
||||
HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
|
||||
ar9285PciePhy_clkreq_always_on_L1, 2);
|
||||
} else if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
|
||||
HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6);
|
||||
HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2);
|
||||
HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
|
||||
@ -162,7 +177,10 @@ ar9280Attach(uint16_t devid, HAL_SOFTC sc,
|
||||
}
|
||||
ar5416AttachPCIE(ah);
|
||||
|
||||
ecode = ath_hal_v14EepromAttach(ah);
|
||||
if (devid == AR9285_DEVID_PCIE)
|
||||
ecode = ath_hal_v4kEepromAttach(ah);
|
||||
else
|
||||
ecode = ath_hal_v14EepromAttach(ah);
|
||||
if (ecode != HAL_OK)
|
||||
goto bad;
|
||||
|
||||
@ -235,7 +253,19 @@ ar9280Attach(uint16_t devid, HAL_SOFTC sc,
|
||||
goto bad; /* XXX ? try to continue */
|
||||
}
|
||||
}
|
||||
if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
|
||||
|
||||
if (AR_SREV_KITE_12_OR_LATER(ah)) {
|
||||
switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
|
||||
case AR5416_EEP_TXGAIN_HIGH_POWER:
|
||||
HAL_INI_INIT(&ahp9280->ah_ini_txgain,
|
||||
ar9285Modes_high_power_tx_gain_v2, 6);
|
||||
break;
|
||||
default:
|
||||
HAL_INI_INIT(&ahp9280->ah_ini_txgain,
|
||||
ar9285Modes_original_tx_gain_v2, 6);
|
||||
break;
|
||||
}
|
||||
} else if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
|
||||
/* setp txgain table */
|
||||
switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
|
||||
case AR5416_EEP_TXGAIN_HIGH_POWER:
|
||||
@ -281,7 +311,7 @@ ar9280Attach(uint16_t devid, HAL_SOFTC sc,
|
||||
OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
|
||||
|
||||
ar9280AniSetup(ah); /* Anti Noise Immunity */
|
||||
ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
|
||||
ar5416InitNfHistBuff(ah, AH5416(ah)->ah_cal.nfCalHist);
|
||||
|
||||
HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
|
||||
|
||||
@ -301,7 +331,10 @@ ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
|
||||
ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
|
||||
OS_DELAY(1000);
|
||||
OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
|
||||
OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
|
||||
if (AR_SREV_KITE(ah))
|
||||
OS_REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
|
||||
else
|
||||
OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
|
||||
}
|
||||
}
|
||||
|
||||
@ -344,6 +377,10 @@ ar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
|
||||
regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain,
|
||||
modesIndex, regWrites);
|
||||
}
|
||||
if (AR_SREV_KITE_12_OR_LATER(ah))
|
||||
regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain,
|
||||
modesIndex, regWrites);
|
||||
|
||||
/* XXX Merlin 100us delay for shift registers */
|
||||
regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
|
||||
1, regWrites);
|
||||
@ -670,7 +707,10 @@ ar9280FillCapabilityInfo(struct ath_hal *ah)
|
||||
|
||||
if (!ar5416FillCapabilityInfo(ah))
|
||||
return AH_FALSE;
|
||||
pCap->halNumGpioPins = 10;
|
||||
if (AR_SREV_KITE_10_OR_LATER(ah))
|
||||
pCap->halNumGpioPins = 12;
|
||||
else
|
||||
pCap->halNumGpioPins = 10;
|
||||
pCap->halWowSupport = AH_TRUE;
|
||||
pCap->halWowMatchPatternExact = AH_TRUE;
|
||||
#if 0
|
||||
@ -730,9 +770,12 @@ ar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
|
||||
static const char*
|
||||
ar9280Probe(uint16_t vendorid, uint16_t devid)
|
||||
{
|
||||
if (vendorid == ATHEROS_VENDOR_ID &&
|
||||
(devid == AR9280_DEVID_PCI || devid == AR9280_DEVID_PCIE))
|
||||
return "Atheros 9280";
|
||||
if (vendorid == ATHEROS_VENDOR_ID) {
|
||||
if (devid == AR9280_DEVID_PCI || devid == AR9280_DEVID_PCIE)
|
||||
return "Atheros 9280";
|
||||
else if (devid == AR9285_DEVID_PCIE)
|
||||
return "Atheros 9285";
|
||||
}
|
||||
return AH_NULL;
|
||||
}
|
||||
AH_CHIP(AR9280, ar9280Probe, ar9280Attach);
|
||||
|
||||
699
sys/dev/ath/ath_hal/ar5416/ar9285.ini
Normal file
699
sys/dev/ath/ath_hal/ar5416/ar9285.ini
Normal file
@ -0,0 +1,699 @@
|
||||
/*
|
||||
* Copyright (c) 2008-2009 Atheros Communications Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/* AR9285 Revsion 10 */
|
||||
static const u_int32_t ar9285Modes[][6] = {
|
||||
{ 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
|
||||
{ 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
|
||||
{ 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
|
||||
{ 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
|
||||
{ 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
|
||||
{ 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
|
||||
{ 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
|
||||
{ 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
|
||||
{ 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
|
||||
{ 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
|
||||
{ 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
|
||||
{ 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
|
||||
{ 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
|
||||
{ 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
|
||||
{ 0x00009844, 0x0372161e, 0x0372161e, 0x03720020, 0x03720020, 0x037216a0 },
|
||||
{ 0x00009848, 0x00001066, 0x00001066, 0x0000004e, 0x0000004e, 0x00001059 },
|
||||
{ 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
|
||||
{ 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
|
||||
{ 0x0000985c, 0x3139605e, 0x3139605e, 0x3136605e, 0x3136605e, 0x3139605e },
|
||||
{ 0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20, 0x00058d18 },
|
||||
{ 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
|
||||
{ 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
|
||||
{ 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
|
||||
{ 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
|
||||
{ 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
|
||||
{ 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
|
||||
{ 0x00009944, 0xdfbc1010, 0xdfbc1010, 0xdfbc1020, 0xdfbc1020, 0xdfbc1010 },
|
||||
{ 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x000099b8, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c },
|
||||
{ 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
|
||||
{ 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
|
||||
{ 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
|
||||
{ 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
|
||||
{ 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
|
||||
{ 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
|
||||
{ 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x00009a00, 0x00000000, 0x00000000, 0x00068084, 0x00068084, 0x00000000 },
|
||||
{ 0x00009a04, 0x00000000, 0x00000000, 0x00068088, 0x00068088, 0x00000000 },
|
||||
{ 0x00009a08, 0x00000000, 0x00000000, 0x0006808c, 0x0006808c, 0x00000000 },
|
||||
{ 0x00009a0c, 0x00000000, 0x00000000, 0x00068100, 0x00068100, 0x00000000 },
|
||||
{ 0x00009a10, 0x00000000, 0x00000000, 0x00068104, 0x00068104, 0x00000000 },
|
||||
{ 0x00009a14, 0x00000000, 0x00000000, 0x00068108, 0x00068108, 0x00000000 },
|
||||
{ 0x00009a18, 0x00000000, 0x00000000, 0x0006810c, 0x0006810c, 0x00000000 },
|
||||
{ 0x00009a1c, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
|
||||
{ 0x00009a20, 0x00000000, 0x00000000, 0x00068114, 0x00068114, 0x00000000 },
|
||||
{ 0x00009a24, 0x00000000, 0x00000000, 0x00068180, 0x00068180, 0x00000000 },
|
||||
{ 0x00009a28, 0x00000000, 0x00000000, 0x00068184, 0x00068184, 0x00000000 },
|
||||
{ 0x00009a2c, 0x00000000, 0x00000000, 0x00068188, 0x00068188, 0x00000000 },
|
||||
{ 0x00009a30, 0x00000000, 0x00000000, 0x0006818c, 0x0006818c, 0x00000000 },
|
||||
{ 0x00009a34, 0x00000000, 0x00000000, 0x00068190, 0x00068190, 0x00000000 },
|
||||
{ 0x00009a38, 0x00000000, 0x00000000, 0x00068194, 0x00068194, 0x00000000 },
|
||||
{ 0x00009a3c, 0x00000000, 0x00000000, 0x000681a0, 0x000681a0, 0x00000000 },
|
||||
{ 0x00009a40, 0x00000000, 0x00000000, 0x0006820c, 0x0006820c, 0x00000000 },
|
||||
{ 0x00009a44, 0x00000000, 0x00000000, 0x000681a8, 0x000681a8, 0x00000000 },
|
||||
{ 0x00009a48, 0x00000000, 0x00000000, 0x00068284, 0x00068284, 0x00000000 },
|
||||
{ 0x00009a4c, 0x00000000, 0x00000000, 0x00068288, 0x00068288, 0x00000000 },
|
||||
{ 0x00009a50, 0x00000000, 0x00000000, 0x00068220, 0x00068220, 0x00000000 },
|
||||
{ 0x00009a54, 0x00000000, 0x00000000, 0x00068290, 0x00068290, 0x00000000 },
|
||||
{ 0x00009a58, 0x00000000, 0x00000000, 0x00068300, 0x00068300, 0x00000000 },
|
||||
{ 0x00009a5c, 0x00000000, 0x00000000, 0x00068304, 0x00068304, 0x00000000 },
|
||||
{ 0x00009a60, 0x00000000, 0x00000000, 0x00068308, 0x00068308, 0x00000000 },
|
||||
{ 0x00009a64, 0x00000000, 0x00000000, 0x0006830c, 0x0006830c, 0x00000000 },
|
||||
{ 0x00009a68, 0x00000000, 0x00000000, 0x00068380, 0x00068380, 0x00000000 },
|
||||
{ 0x00009a6c, 0x00000000, 0x00000000, 0x00068384, 0x00068384, 0x00000000 },
|
||||
{ 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
|
||||
{ 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
|
||||
{ 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
|
||||
{ 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
|
||||
{ 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
|
||||
{ 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
|
||||
{ 0x00009a88, 0x00000000, 0x00000000, 0x00068b04, 0x00068b04, 0x00000000 },
|
||||
{ 0x00009a8c, 0x00000000, 0x00000000, 0x00068b08, 0x00068b08, 0x00000000 },
|
||||
{ 0x00009a90, 0x00000000, 0x00000000, 0x00068b08, 0x00068b08, 0x00000000 },
|
||||
{ 0x00009a94, 0x00000000, 0x00000000, 0x00068b0c, 0x00068b0c, 0x00000000 },
|
||||
{ 0x00009a98, 0x00000000, 0x00000000, 0x00068b80, 0x00068b80, 0x00000000 },
|
||||
{ 0x00009a9c, 0x00000000, 0x00000000, 0x00068b84, 0x00068b84, 0x00000000 },
|
||||
{ 0x00009aa0, 0x00000000, 0x00000000, 0x00068b88, 0x00068b88, 0x00000000 },
|
||||
{ 0x00009aa4, 0x00000000, 0x00000000, 0x00068b8c, 0x00068b8c, 0x00000000 },
|
||||
{ 0x00009aa8, 0x00000000, 0x00000000, 0x000b8b90, 0x000b8b90, 0x00000000 },
|
||||
{ 0x00009aac, 0x00000000, 0x00000000, 0x000b8f80, 0x000b8f80, 0x00000000 },
|
||||
{ 0x00009ab0, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
|
||||
{ 0x00009ab4, 0x00000000, 0x00000000, 0x000b8f88, 0x000b8f88, 0x00000000 },
|
||||
{ 0x00009ab8, 0x00000000, 0x00000000, 0x000b8f8c, 0x000b8f8c, 0x00000000 },
|
||||
{ 0x00009abc, 0x00000000, 0x00000000, 0x000b8f90, 0x000b8f90, 0x00000000 },
|
||||
{ 0x00009ac0, 0x00000000, 0x00000000, 0x000bb30c, 0x000bb30c, 0x00000000 },
|
||||
{ 0x00009ac4, 0x00000000, 0x00000000, 0x000bb310, 0x000bb310, 0x00000000 },
|
||||
{ 0x00009ac8, 0x00000000, 0x00000000, 0x000bb384, 0x000bb384, 0x00000000 },
|
||||
{ 0x00009acc, 0x00000000, 0x00000000, 0x000bb388, 0x000bb388, 0x00000000 },
|
||||
{ 0x00009ad0, 0x00000000, 0x00000000, 0x000bb324, 0x000bb324, 0x00000000 },
|
||||
{ 0x00009ad4, 0x00000000, 0x00000000, 0x000bb704, 0x000bb704, 0x00000000 },
|
||||
{ 0x00009ad8, 0x00000000, 0x00000000, 0x000f96a4, 0x000f96a4, 0x00000000 },
|
||||
{ 0x00009adc, 0x00000000, 0x00000000, 0x000f96a8, 0x000f96a8, 0x00000000 },
|
||||
{ 0x00009ae0, 0x00000000, 0x00000000, 0x000f9710, 0x000f9710, 0x00000000 },
|
||||
{ 0x00009ae4, 0x00000000, 0x00000000, 0x000f9714, 0x000f9714, 0x00000000 },
|
||||
{ 0x00009ae8, 0x00000000, 0x00000000, 0x000f9720, 0x000f9720, 0x00000000 },
|
||||
{ 0x00009aec, 0x00000000, 0x00000000, 0x000f9724, 0x000f9724, 0x00000000 },
|
||||
{ 0x00009af0, 0x00000000, 0x00000000, 0x000f9728, 0x000f9728, 0x00000000 },
|
||||
{ 0x00009af4, 0x00000000, 0x00000000, 0x000f972c, 0x000f972c, 0x00000000 },
|
||||
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{ 0x00009b40, 0x00000000, 0x00000000, 0x000fb7ca, 0x000fb7ca, 0x00000000 },
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{ 0x00009b44, 0x00000000, 0x00000000, 0x000fb7ce, 0x000fb7ce, 0x00000000 },
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{ 0x00009b48, 0x00000000, 0x00000000, 0x000fb7d2, 0x000fb7d2, 0x00000000 },
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{ 0x00009b5c, 0x00000000, 0x00000000, 0x000fb7cf, 0x000fb7cf, 0x00000000 },
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{ 0x00009b60, 0x00000000, 0x00000000, 0x000fb7d7, 0x000fb7d7, 0x00000000 },
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{ 0x00009b64, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009b68, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009b6c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009b70, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009b74, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009b78, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009b7c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009b80, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009b84, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009b88, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009b8c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009b90, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009b94, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009b98, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009b9c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009ba0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009ba4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009ba8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009bac, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009bb0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009bb4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009bb8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009bbc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009bc0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009bc4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009bc8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009bcc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009bd0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009bd4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009bd8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009bdc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009be0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009be4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009be8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009bec, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009bf0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009bf4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009bf8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x00009bfc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
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{ 0x0000aa00, 0x00000000, 0x00000000, 0x0006801c, 0x0006801c, 0x00000000 },
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{ 0x0000aa04, 0x00000000, 0x00000000, 0x00068080, 0x00068080, 0x00000000 },
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{ 0x0000aa08, 0x00000000, 0x00000000, 0x00068084, 0x00068084, 0x00000000 },
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{ 0x0000aa0c, 0x00000000, 0x00000000, 0x00068088, 0x00068088, 0x00000000 },
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{ 0x0000aa10, 0x00000000, 0x00000000, 0x0006808c, 0x0006808c, 0x00000000 },
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{ 0x0000aa14, 0x00000000, 0x00000000, 0x00068100, 0x00068100, 0x00000000 },
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{ 0x0000aa18, 0x00000000, 0x00000000, 0x00068104, 0x00068104, 0x00000000 },
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{ 0x0000aa1c, 0x00000000, 0x00000000, 0x00068108, 0x00068108, 0x00000000 },
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{ 0x0000aa20, 0x00000000, 0x00000000, 0x0006810c, 0x0006810c, 0x00000000 },
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{ 0x0000aa3c, 0x00000000, 0x00000000, 0x00068190, 0x00068190, 0x00000000 },
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{ 0x0000aa44, 0x00000000, 0x00000000, 0x000681a0, 0x000681a0, 0x00000000 },
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{ 0x0000aa4c, 0x00000000, 0x00000000, 0x000681a8, 0x000681a8, 0x00000000 },
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{ 0x0000aa7c, 0x00000000, 0x00000000, 0x00068794, 0x00068794, 0x00000000 },
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{ 0x0000aa8c, 0x00000000, 0x00000000, 0x00068b8d, 0x00068b8d, 0x00000000 },
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{ 0x0000aab4, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
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{ 0x0000aab8, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
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{ 0x0000aabc, 0x00000000, 0x00000000, 0x000b8f88, 0x000b8f88, 0x00000000 },
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{ 0x0000aac8, 0x00000000, 0x00000000, 0x000bb388, 0x000bb388, 0x00000000 },
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{ 0x0000aacc, 0x00000000, 0x00000000, 0x000bb38c, 0x000bb38c, 0x00000000 },
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{ 0x0000aad0, 0x00000000, 0x00000000, 0x000bb394, 0x000bb394, 0x00000000 },
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{ 0x0000aad4, 0x00000000, 0x00000000, 0x000bb798, 0x000bb798, 0x00000000 },
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{ 0x0000aad8, 0x00000000, 0x00000000, 0x000f970c, 0x000f970c, 0x00000000 },
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{ 0x0000aadc, 0x00000000, 0x00000000, 0x000f9710, 0x000f9710, 0x00000000 },
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{ 0x0000aae0, 0x00000000, 0x00000000, 0x000f9714, 0x000f9714, 0x00000000 },
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{ 0x0000aae4, 0x00000000, 0x00000000, 0x000f9718, 0x000f9718, 0x00000000 },
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{ 0x0000aae8, 0x00000000, 0x00000000, 0x000f9705, 0x000f9705, 0x00000000 },
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{ 0x0000aaec, 0x00000000, 0x00000000, 0x000f9709, 0x000f9709, 0x00000000 },
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{ 0x0000aaf0, 0x00000000, 0x00000000, 0x000f970d, 0x000f970d, 0x00000000 },
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{ 0x0000aaf4, 0x00000000, 0x00000000, 0x000f9711, 0x000f9711, 0x00000000 },
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{ 0x0000aaf8, 0x00000000, 0x00000000, 0x000f9715, 0x000f9715, 0x00000000 },
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{ 0x0000aafc, 0x00000000, 0x00000000, 0x000f9719, 0x000f9719, 0x00000000 },
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{ 0x0000ab00, 0x00000000, 0x00000000, 0x000fb7a4, 0x000fb7a4, 0x00000000 },
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{ 0x0000ab04, 0x00000000, 0x00000000, 0x000fb7a8, 0x000fb7a8, 0x00000000 },
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{ 0x0000ab08, 0x00000000, 0x00000000, 0x000fb7ac, 0x000fb7ac, 0x00000000 },
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{ 0x0000ab0c, 0x00000000, 0x00000000, 0x000fb7ac, 0x000fb7ac, 0x00000000 },
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{ 0x0000ab10, 0x00000000, 0x00000000, 0x000fb7b0, 0x000fb7b0, 0x00000000 },
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{ 0x0000ab14, 0x00000000, 0x00000000, 0x000fb7b8, 0x000fb7b8, 0x00000000 },
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{ 0x0000ab18, 0x00000000, 0x00000000, 0x000fb7bc, 0x000fb7bc, 0x00000000 },
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{ 0x0000ab1c, 0x00000000, 0x00000000, 0x000fb7a1, 0x000fb7a1, 0x00000000 },
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{ 0x0000ab20, 0x00000000, 0x00000000, 0x000fb7a5, 0x000fb7a5, 0x00000000 },
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{ 0x0000ab24, 0x00000000, 0x00000000, 0x000fb7a9, 0x000fb7a9, 0x00000000 },
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{ 0x0000ab28, 0x00000000, 0x00000000, 0x000fb7b1, 0x000fb7b1, 0x00000000 },
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{ 0x0000ab2c, 0x00000000, 0x00000000, 0x000fb7b5, 0x000fb7b5, 0x00000000 },
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{ 0x0000ab30, 0x00000000, 0x00000000, 0x000fb7bd, 0x000fb7bd, 0x00000000 },
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{ 0x0000ab34, 0x00000000, 0x00000000, 0x000fb7c9, 0x000fb7c9, 0x00000000 },
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{ 0x0000ab38, 0x00000000, 0x00000000, 0x000fb7cd, 0x000fb7cd, 0x00000000 },
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{ 0x0000ab3c, 0x00000000, 0x00000000, 0x000fb7d1, 0x000fb7d1, 0x00000000 },
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{ 0x0000ab40, 0x00000000, 0x00000000, 0x000fb7d9, 0x000fb7d9, 0x00000000 },
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{ 0x0000ab44, 0x00000000, 0x00000000, 0x000fb7c2, 0x000fb7c2, 0x00000000 },
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{ 0x0000ab48, 0x00000000, 0x00000000, 0x000fb7c6, 0x000fb7c6, 0x00000000 },
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{ 0x0000ab4c, 0x00000000, 0x00000000, 0x000fb7ca, 0x000fb7ca, 0x00000000 },
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{ 0x0000ab50, 0x00000000, 0x00000000, 0x000fb7ce, 0x000fb7ce, 0x00000000 },
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{ 0x0000ab54, 0x00000000, 0x00000000, 0x000fb7d2, 0x000fb7d2, 0x00000000 },
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{ 0x0000ab58, 0x00000000, 0x00000000, 0x000fb7d6, 0x000fb7d6, 0x00000000 },
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{ 0x0000ab5c, 0x00000000, 0x00000000, 0x000fb7c3, 0x000fb7c3, 0x00000000 },
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{ 0x0000ab60, 0x00000000, 0x00000000, 0x000fb7cb, 0x000fb7cb, 0x00000000 },
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{ 0x0000ab64, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000ab68, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000ab6c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000ab70, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000ab74, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000ab78, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000ab7c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000ab80, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000ab84, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000ab88, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000ab8c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000ab90, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000ab94, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000ab98, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000ab9c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000aba0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000aba4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000aba8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000abac, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000abb0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000abb4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000abb8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000abbc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000abc0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000abc4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000abc8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000abcc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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||||
{ 0x0000abd0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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||||
{ 0x0000abd4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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{ 0x0000abd8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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||||
{ 0x0000abdc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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||||
{ 0x0000abe0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
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||||
{ 0x0000abe4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abe8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abec, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abf0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abf4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abf8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abfc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
|
||||
{ 0x0000a20c, 0x00000014, 0x00000014, 0x00000000, 0x00000000, 0x0001f000 },
|
||||
{ 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
|
||||
{ 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
|
||||
{ 0x0000a250, 0x001ff000, 0x001ff000, 0x001ca000, 0x001ca000, 0x001da000 },
|
||||
{ 0x0000a274, 0x0a81c652, 0x0a81c652, 0x0a820652, 0x0a820652, 0x0a82a652 },
|
||||
{ 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x0000a304, 0x00000000, 0x00000000, 0x00007201, 0x00007201, 0x00000000 },
|
||||
{ 0x0000a308, 0x00000000, 0x00000000, 0x00010408, 0x00010408, 0x00000000 },
|
||||
{ 0x0000a30c, 0x00000000, 0x00000000, 0x0001860a, 0x0001860a, 0x00000000 },
|
||||
{ 0x0000a310, 0x00000000, 0x00000000, 0x00020818, 0x00020818, 0x00000000 },
|
||||
{ 0x0000a314, 0x00000000, 0x00000000, 0x00024858, 0x00024858, 0x00000000 },
|
||||
{ 0x0000a318, 0x00000000, 0x00000000, 0x00026859, 0x00026859, 0x00000000 },
|
||||
{ 0x0000a31c, 0x00000000, 0x00000000, 0x0002985b, 0x0002985b, 0x00000000 },
|
||||
{ 0x0000a320, 0x00000000, 0x00000000, 0x0002c89a, 0x0002c89a, 0x00000000 },
|
||||
{ 0x0000a324, 0x00000000, 0x00000000, 0x0002e89b, 0x0002e89b, 0x00000000 },
|
||||
{ 0x0000a328, 0x00000000, 0x00000000, 0x0003089c, 0x0003089c, 0x00000000 },
|
||||
{ 0x0000a32c, 0x00000000, 0x00000000, 0x0003289d, 0x0003289d, 0x00000000 },
|
||||
{ 0x0000a330, 0x00000000, 0x00000000, 0x0003489e, 0x0003489e, 0x00000000 },
|
||||
{ 0x0000a334, 0x00000000, 0x00000000, 0x000388de, 0x000388de, 0x00000000 },
|
||||
{ 0x0000a338, 0x00000000, 0x00000000, 0x0003b91e, 0x0003b91e, 0x00000000 },
|
||||
{ 0x0000a33c, 0x00000000, 0x00000000, 0x0003d95e, 0x0003d95e, 0x00000000 },
|
||||
{ 0x0000a340, 0x00000000, 0x00000000, 0x000419df, 0x000419df, 0x00000000 },
|
||||
{ 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
|
||||
};
|
||||
|
||||
static const u_int32_t ar9285Common[][2] = {
|
||||
{ 0x0000000c, 0x00000000 },
|
||||
{ 0x00000030, 0x00020045 },
|
||||
{ 0x00000034, 0x00000005 },
|
||||
{ 0x00000040, 0x00000000 },
|
||||
{ 0x00000044, 0x00000008 },
|
||||
{ 0x00000048, 0x00000008 },
|
||||
{ 0x0000004c, 0x00000010 },
|
||||
{ 0x00000050, 0x00000000 },
|
||||
{ 0x00000054, 0x0000001f },
|
||||
{ 0x00000800, 0x00000000 },
|
||||
{ 0x00000804, 0x00000000 },
|
||||
{ 0x00000808, 0x00000000 },
|
||||
{ 0x0000080c, 0x00000000 },
|
||||
{ 0x00000810, 0x00000000 },
|
||||
{ 0x00000814, 0x00000000 },
|
||||
{ 0x00000818, 0x00000000 },
|
||||
{ 0x0000081c, 0x00000000 },
|
||||
{ 0x00000820, 0x00000000 },
|
||||
{ 0x00000824, 0x00000000 },
|
||||
{ 0x00001040, 0x002ffc0f },
|
||||
{ 0x00001044, 0x002ffc0f },
|
||||
{ 0x00001048, 0x002ffc0f },
|
||||
{ 0x0000104c, 0x002ffc0f },
|
||||
{ 0x00001050, 0x002ffc0f },
|
||||
{ 0x00001054, 0x002ffc0f },
|
||||
{ 0x00001058, 0x002ffc0f },
|
||||
{ 0x0000105c, 0x002ffc0f },
|
||||
{ 0x00001060, 0x002ffc0f },
|
||||
{ 0x00001064, 0x002ffc0f },
|
||||
{ 0x00001230, 0x00000000 },
|
||||
{ 0x00001270, 0x00000000 },
|
||||
{ 0x00001038, 0x00000000 },
|
||||
{ 0x00001078, 0x00000000 },
|
||||
{ 0x000010b8, 0x00000000 },
|
||||
{ 0x000010f8, 0x00000000 },
|
||||
{ 0x00001138, 0x00000000 },
|
||||
{ 0x00001178, 0x00000000 },
|
||||
{ 0x000011b8, 0x00000000 },
|
||||
{ 0x000011f8, 0x00000000 },
|
||||
{ 0x00001238, 0x00000000 },
|
||||
{ 0x00001278, 0x00000000 },
|
||||
{ 0x000012b8, 0x00000000 },
|
||||
{ 0x000012f8, 0x00000000 },
|
||||
{ 0x00001338, 0x00000000 },
|
||||
{ 0x00001378, 0x00000000 },
|
||||
{ 0x000013b8, 0x00000000 },
|
||||
{ 0x000013f8, 0x00000000 },
|
||||
{ 0x00001438, 0x00000000 },
|
||||
{ 0x00001478, 0x00000000 },
|
||||
{ 0x000014b8, 0x00000000 },
|
||||
{ 0x000014f8, 0x00000000 },
|
||||
{ 0x00001538, 0x00000000 },
|
||||
{ 0x00001578, 0x00000000 },
|
||||
{ 0x000015b8, 0x00000000 },
|
||||
{ 0x000015f8, 0x00000000 },
|
||||
{ 0x00001638, 0x00000000 },
|
||||
{ 0x00001678, 0x00000000 },
|
||||
{ 0x000016b8, 0x00000000 },
|
||||
{ 0x000016f8, 0x00000000 },
|
||||
{ 0x00001738, 0x00000000 },
|
||||
{ 0x00001778, 0x00000000 },
|
||||
{ 0x000017b8, 0x00000000 },
|
||||
{ 0x000017f8, 0x00000000 },
|
||||
{ 0x0000103c, 0x00000000 },
|
||||
{ 0x0000107c, 0x00000000 },
|
||||
{ 0x000010bc, 0x00000000 },
|
||||
{ 0x000010fc, 0x00000000 },
|
||||
{ 0x0000113c, 0x00000000 },
|
||||
{ 0x0000117c, 0x00000000 },
|
||||
{ 0x000011bc, 0x00000000 },
|
||||
{ 0x000011fc, 0x00000000 },
|
||||
{ 0x0000123c, 0x00000000 },
|
||||
{ 0x0000127c, 0x00000000 },
|
||||
{ 0x000012bc, 0x00000000 },
|
||||
{ 0x000012fc, 0x00000000 },
|
||||
{ 0x0000133c, 0x00000000 },
|
||||
{ 0x0000137c, 0x00000000 },
|
||||
{ 0x000013bc, 0x00000000 },
|
||||
{ 0x000013fc, 0x00000000 },
|
||||
{ 0x0000143c, 0x00000000 },
|
||||
{ 0x0000147c, 0x00000000 },
|
||||
{ 0x00004030, 0x00000002 },
|
||||
{ 0x0000403c, 0x00000002 },
|
||||
{ 0x00004024, 0x0000001f },
|
||||
{ 0x00004060, 0x00000000 },
|
||||
{ 0x00004064, 0x00000000 },
|
||||
{ 0x00007010, 0x00000031 },
|
||||
{ 0x00007034, 0x00000002 },
|
||||
{ 0x00007038, 0x000004c2 },
|
||||
{ 0x00008004, 0x00000000 },
|
||||
{ 0x00008008, 0x00000000 },
|
||||
{ 0x0000800c, 0x00000000 },
|
||||
{ 0x00008018, 0x00000700 },
|
||||
{ 0x00008020, 0x00000000 },
|
||||
{ 0x00008038, 0x00000000 },
|
||||
{ 0x0000803c, 0x00000000 },
|
||||
{ 0x00008048, 0x00000000 },
|
||||
{ 0x00008054, 0x00000000 },
|
||||
{ 0x00008058, 0x00000000 },
|
||||
{ 0x0000805c, 0x000fc78f },
|
||||
{ 0x00008060, 0x0000000f },
|
||||
{ 0x00008064, 0x00000000 },
|
||||
{ 0x00008070, 0x00000000 },
|
||||
{ 0x000080c0, 0x2a80001a },
|
||||
{ 0x000080c4, 0x05dc01e0 },
|
||||
{ 0x000080c8, 0x1f402710 },
|
||||
{ 0x000080cc, 0x01f40000 },
|
||||
{ 0x000080d0, 0x00001e00 },
|
||||
{ 0x000080d4, 0x00000000 },
|
||||
{ 0x000080d8, 0x00400000 },
|
||||
{ 0x000080e0, 0xffffffff },
|
||||
{ 0x000080e4, 0x0000ffff },
|
||||
{ 0x000080e8, 0x003f3f3f },
|
||||
{ 0x000080ec, 0x00000000 },
|
||||
{ 0x000080f0, 0x00000000 },
|
||||
{ 0x000080f4, 0x00000000 },
|
||||
{ 0x000080f8, 0x00000000 },
|
||||
{ 0x000080fc, 0x00020000 },
|
||||
{ 0x00008100, 0x00020000 },
|
||||
{ 0x00008104, 0x00000001 },
|
||||
{ 0x00008108, 0x00000052 },
|
||||
{ 0x0000810c, 0x00000000 },
|
||||
{ 0x00008110, 0x00000168 },
|
||||
{ 0x00008118, 0x000100aa },
|
||||
{ 0x0000811c, 0x00003210 },
|
||||
{ 0x00008120, 0x08f04800 },
|
||||
{ 0x00008124, 0x00000000 },
|
||||
{ 0x00008128, 0x00000000 },
|
||||
{ 0x0000812c, 0x00000000 },
|
||||
{ 0x00008130, 0x00000000 },
|
||||
{ 0x00008134, 0x00000000 },
|
||||
{ 0x00008138, 0x00000000 },
|
||||
{ 0x0000813c, 0x00000000 },
|
||||
{ 0x00008144, 0x00000000 },
|
||||
{ 0x00008168, 0x00000000 },
|
||||
{ 0x0000816c, 0x00000000 },
|
||||
{ 0x00008170, 0x32143320 },
|
||||
{ 0x00008174, 0xfaa4fa50 },
|
||||
{ 0x00008178, 0x00000100 },
|
||||
{ 0x0000817c, 0x00000000 },
|
||||
{ 0x000081c0, 0x00000000 },
|
||||
{ 0x000081d0, 0x00003210 },
|
||||
{ 0x000081ec, 0x00000000 },
|
||||
{ 0x000081f0, 0x00000000 },
|
||||
{ 0x000081f4, 0x00000000 },
|
||||
{ 0x000081f8, 0x00000000 },
|
||||
{ 0x000081fc, 0x00000000 },
|
||||
{ 0x00008200, 0x00000000 },
|
||||
{ 0x00008204, 0x00000000 },
|
||||
{ 0x00008208, 0x00000000 },
|
||||
{ 0x0000820c, 0x00000000 },
|
||||
{ 0x00008210, 0x00000000 },
|
||||
{ 0x00008214, 0x00000000 },
|
||||
{ 0x00008218, 0x00000000 },
|
||||
{ 0x0000821c, 0x00000000 },
|
||||
{ 0x00008220, 0x00000000 },
|
||||
{ 0x00008224, 0x00000000 },
|
||||
{ 0x00008228, 0x00000000 },
|
||||
{ 0x0000822c, 0x00000000 },
|
||||
{ 0x00008230, 0x00000000 },
|
||||
{ 0x00008234, 0x00000000 },
|
||||
{ 0x00008238, 0x00000000 },
|
||||
{ 0x0000823c, 0x00000000 },
|
||||
{ 0x00008240, 0x00100000 },
|
||||
{ 0x00008244, 0x0010f400 },
|
||||
{ 0x00008248, 0x00000100 },
|
||||
{ 0x0000824c, 0x0001e800 },
|
||||
{ 0x00008250, 0x00000000 },
|
||||
{ 0x00008254, 0x00000000 },
|
||||
{ 0x00008258, 0x00000000 },
|
||||
{ 0x0000825c, 0x400000ff },
|
||||
{ 0x00008260, 0x00080922 },
|
||||
{ 0x00008264, 0xa8a00010 },
|
||||
{ 0x00008270, 0x00000000 },
|
||||
{ 0x00008274, 0x40000000 },
|
||||
{ 0x00008278, 0x003e4180 },
|
||||
{ 0x0000827c, 0x00000000 },
|
||||
{ 0x00008284, 0x0000002c },
|
||||
{ 0x00008288, 0x0000002c },
|
||||
{ 0x0000828c, 0x00000000 },
|
||||
{ 0x00008294, 0x00000000 },
|
||||
{ 0x00008298, 0x00000000 },
|
||||
{ 0x0000829c, 0x00000000 },
|
||||
{ 0x00008300, 0x00000040 },
|
||||
{ 0x00008314, 0x00000000 },
|
||||
{ 0x00008328, 0x00000000 },
|
||||
{ 0x0000832c, 0x00000001 },
|
||||
{ 0x00008330, 0x00000302 },
|
||||
{ 0x00008334, 0x00000e00 },
|
||||
{ 0x00008338, 0x00000000 },
|
||||
{ 0x0000833c, 0x00000000 },
|
||||
{ 0x00008340, 0x00010380 },
|
||||
{ 0x00008344, 0x00481043 },
|
||||
{ 0x00009808, 0x00000000 },
|
||||
{ 0x0000980c, 0xafe68e30 },
|
||||
{ 0x00009810, 0xfd14e000 },
|
||||
{ 0x00009814, 0x9c0a9f6b },
|
||||
{ 0x0000981c, 0x00000000 },
|
||||
{ 0x0000982c, 0x0000a000 },
|
||||
{ 0x00009830, 0x00000000 },
|
||||
{ 0x0000983c, 0x00200400 },
|
||||
{ 0x0000984c, 0x0040233c },
|
||||
{ 0x00009854, 0x00000044 },
|
||||
{ 0x00009900, 0x00000000 },
|
||||
{ 0x00009904, 0x00000000 },
|
||||
{ 0x00009908, 0x00000000 },
|
||||
{ 0x0000990c, 0x00000000 },
|
||||
{ 0x00009910, 0x01002310 },
|
||||
{ 0x0000991c, 0x10000fff },
|
||||
{ 0x00009920, 0x04900000 },
|
||||
{ 0x00009928, 0x00000001 },
|
||||
{ 0x0000992c, 0x00000004 },
|
||||
{ 0x00009934, 0x1e1f2022 },
|
||||
{ 0x00009938, 0x0a0b0c0d },
|
||||
{ 0x0000993c, 0x00000000 },
|
||||
{ 0x00009940, 0x14750604 },
|
||||
{ 0x00009948, 0x9280c00a },
|
||||
{ 0x0000994c, 0x00020028 },
|
||||
{ 0x00009954, 0x5f3ca3de },
|
||||
{ 0x00009958, 0x2108ecff },
|
||||
{ 0x00009968, 0x000003ce },
|
||||
{ 0x00009970, 0x1927b515 },
|
||||
{ 0x00009974, 0x00000000 },
|
||||
{ 0x00009978, 0x00000001 },
|
||||
{ 0x0000997c, 0x00000000 },
|
||||
{ 0x00009980, 0x00000000 },
|
||||
{ 0x00009984, 0x00000000 },
|
||||
{ 0x00009988, 0x00000000 },
|
||||
{ 0x0000998c, 0x00000000 },
|
||||
{ 0x00009990, 0x00000000 },
|
||||
{ 0x00009994, 0x00000000 },
|
||||
{ 0x00009998, 0x00000000 },
|
||||
{ 0x0000999c, 0x00000000 },
|
||||
{ 0x000099a0, 0x00000000 },
|
||||
{ 0x000099a4, 0x00000001 },
|
||||
{ 0x000099a8, 0x201fff00 },
|
||||
{ 0x000099ac, 0x2def0a00 },
|
||||
{ 0x000099b0, 0x03051000 },
|
||||
{ 0x000099b4, 0x00000820 },
|
||||
{ 0x000099dc, 0x00000000 },
|
||||
{ 0x000099e0, 0x00000000 },
|
||||
{ 0x000099e4, 0xaaaaaaaa },
|
||||
{ 0x000099e8, 0x3c466478 },
|
||||
{ 0x000099ec, 0x0cc80caa },
|
||||
{ 0x000099f0, 0x00000000 },
|
||||
{ 0x0000a208, 0x803e6788 },
|
||||
{ 0x0000a210, 0x4080a333 },
|
||||
{ 0x0000a214, 0x00206c10 },
|
||||
{ 0x0000a218, 0x009c4060 },
|
||||
{ 0x0000a220, 0x01834061 },
|
||||
{ 0x0000a224, 0x00000400 },
|
||||
{ 0x0000a228, 0x000003b5 },
|
||||
{ 0x0000a22c, 0x00000000 },
|
||||
{ 0x0000a234, 0x20202020 },
|
||||
{ 0x0000a238, 0x20202020 },
|
||||
{ 0x0000a244, 0x00000000 },
|
||||
{ 0x0000a248, 0xfffffffc },
|
||||
{ 0x0000a24c, 0x00000000 },
|
||||
{ 0x0000a254, 0x00000000 },
|
||||
{ 0x0000a258, 0x0ccb5380 },
|
||||
{ 0x0000a25c, 0x15151501 },
|
||||
{ 0x0000a260, 0xdfa90f01 },
|
||||
{ 0x0000a268, 0x00000000 },
|
||||
{ 0x0000a26c, 0x0ebae9e6 },
|
||||
{ 0x0000d270, 0x0d820820 },
|
||||
{ 0x0000a278, 0x39ce739c },
|
||||
{ 0x0000a27c, 0x050e039c },
|
||||
{ 0x0000d35c, 0x07ffffef },
|
||||
{ 0x0000d360, 0x0fffffe7 },
|
||||
{ 0x0000d364, 0x17ffffe5 },
|
||||
{ 0x0000d368, 0x1fffffe4 },
|
||||
{ 0x0000d36c, 0x37ffffe3 },
|
||||
{ 0x0000d370, 0x3fffffe3 },
|
||||
{ 0x0000d374, 0x57ffffe3 },
|
||||
{ 0x0000d378, 0x5fffffe2 },
|
||||
{ 0x0000d37c, 0x7fffffe2 },
|
||||
{ 0x0000d380, 0x7f3c7bba },
|
||||
{ 0x0000d384, 0xf3307ff0 },
|
||||
{ 0x0000a388, 0x0c000000 },
|
||||
{ 0x0000a38c, 0x20202020 },
|
||||
{ 0x0000a390, 0x20202020 },
|
||||
{ 0x0000a394, 0x39ce739c },
|
||||
{ 0x0000a398, 0x0000039c },
|
||||
{ 0x0000a39c, 0x00000001 },
|
||||
{ 0x0000a3a0, 0x00000000 },
|
||||
{ 0x0000a3a4, 0x00000000 },
|
||||
{ 0x0000a3a8, 0x00000000 },
|
||||
{ 0x0000a3ac, 0x00000000 },
|
||||
{ 0x0000a3b0, 0x00000000 },
|
||||
{ 0x0000a3b4, 0x00000000 },
|
||||
{ 0x0000a3b8, 0x00000000 },
|
||||
{ 0x0000a3bc, 0x00000000 },
|
||||
{ 0x0000a3c0, 0x00000000 },
|
||||
{ 0x0000a3c4, 0x00000000 },
|
||||
{ 0x0000a3cc, 0x20202020 },
|
||||
{ 0x0000a3d0, 0x20202020 },
|
||||
{ 0x0000a3d4, 0x20202020 },
|
||||
{ 0x0000a3dc, 0x39ce739c },
|
||||
{ 0x0000a3e0, 0x0000039c },
|
||||
{ 0x0000a3e4, 0x00000000 },
|
||||
{ 0x0000a3e8, 0x18c43433 },
|
||||
{ 0x0000a3ec, 0x00f70081 },
|
||||
{ 0x00007800, 0x00140000 },
|
||||
{ 0x00007804, 0x0e4548d8 },
|
||||
{ 0x00007808, 0x54214514 },
|
||||
{ 0x0000780c, 0x02025820 },
|
||||
{ 0x00007810, 0x71c0d388 },
|
||||
{ 0x00007814, 0x924934a8 },
|
||||
{ 0x0000781c, 0x00000000 },
|
||||
{ 0x00007820, 0x00000c04 },
|
||||
{ 0x00007824, 0x00d86fff },
|
||||
{ 0x00007828, 0x26d2491b },
|
||||
{ 0x0000782c, 0x6e36d97b },
|
||||
{ 0x00007830, 0xedb6d96c },
|
||||
{ 0x00007834, 0x71400086 },
|
||||
{ 0x00007838, 0xfac68800 },
|
||||
{ 0x0000783c, 0x0001fffe },
|
||||
{ 0x00007840, 0xffeb1a20 },
|
||||
{ 0x00007844, 0x000c0db6 },
|
||||
{ 0x00007848, 0x6db61b6f },
|
||||
{ 0x0000784c, 0x6d9b66db },
|
||||
{ 0x00007850, 0x6d8c6dba },
|
||||
{ 0x00007854, 0x00040000 },
|
||||
{ 0x00007858, 0xdb003012 },
|
||||
{ 0x0000785c, 0x04924914 },
|
||||
{ 0x00007860, 0x21084210 },
|
||||
{ 0x00007864, 0xf7d7ffde },
|
||||
{ 0x00007868, 0xc2034080 },
|
||||
{ 0x0000786c, 0x48609eb4 },
|
||||
{ 0x00007870, 0x10142c00 },
|
||||
};
|
||||
|
||||
static const u_int32_t ar9285PciePhy_clkreq_always_on_L1[][2] = {
|
||||
{0x00004040, 0x9248fd00 },
|
||||
{0x00004040, 0x24924924 },
|
||||
{0x00004040, 0xa8000019 },
|
||||
{0x00004040, 0x13160820 },
|
||||
{0x00004040, 0xe5980560 },
|
||||
{0x00004040, 0xc01dcffd },
|
||||
{0x00004040, 0x1aaabe41 },
|
||||
{0x00004040, 0xbe105554 },
|
||||
{0x00004040, 0x00043007 },
|
||||
{0x00004044, 0x00000000 },
|
||||
};
|
||||
|
||||
static const u_int32_t ar9285PciePhy_clkreq_off_L1[][2] = {
|
||||
{0x00004040, 0x9248fd00 },
|
||||
{0x00004040, 0x24924924 },
|
||||
{0x00004040, 0xa8000019 },
|
||||
{0x00004040, 0x13160820 },
|
||||
{0x00004040, 0xe5980560 },
|
||||
{0x00004040, 0xc01dcffc },
|
||||
{0x00004040, 0x1aaabe41 },
|
||||
{0x00004040, 0xbe105554 },
|
||||
{0x00004040, 0x00043007 },
|
||||
{0x00004044, 0x00000000 },
|
||||
};
|
||||
746
sys/dev/ath/ath_hal/ar5416/ar9285v2.ini
Normal file
746
sys/dev/ath/ath_hal/ar5416/ar9285v2.ini
Normal file
@ -0,0 +1,746 @@
|
||||
/*
|
||||
* Copyright (c) 2008-2009 Atheros Communications Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/* AR9285 v1_2 PCI Register Writes. Created: 04/13/09 */
|
||||
static const u_int32_t ar9285Modes_v2[][6] = {
|
||||
/* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
|
||||
{ 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
|
||||
{ 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
|
||||
{ 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
|
||||
{ 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
|
||||
{ 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
|
||||
{ 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
|
||||
{ 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
|
||||
{ 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
|
||||
{ 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
|
||||
{ 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
|
||||
{ 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
|
||||
{ 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
|
||||
{ 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
|
||||
{ 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
|
||||
{ 0x00009844, 0x0372161e, 0x0372161e, 0x03721620, 0x03721620, 0x037216a0 },
|
||||
{ 0x00009848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
|
||||
{ 0x0000a848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
|
||||
{ 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
|
||||
{ 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
|
||||
{ 0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e },
|
||||
{ 0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20, 0x00058d18 },
|
||||
{ 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
|
||||
{ 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
|
||||
{ 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
|
||||
{ 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
|
||||
{ 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
|
||||
{ 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
|
||||
{ 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1020, 0xffbc1020, 0xffbc1010 },
|
||||
{ 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x000099b8, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c },
|
||||
{ 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
|
||||
{ 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
|
||||
{ 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
|
||||
{ 0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f },
|
||||
{ 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
|
||||
{ 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
|
||||
{ 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x00009a00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
|
||||
{ 0x00009a04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
|
||||
{ 0x00009a08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
|
||||
{ 0x00009a0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
|
||||
{ 0x00009a10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
|
||||
{ 0x00009a14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
|
||||
{ 0x00009a18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
|
||||
{ 0x00009a1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
|
||||
{ 0x00009a20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
|
||||
{ 0x00009a24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
|
||||
{ 0x00009a28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
|
||||
{ 0x00009a2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
|
||||
{ 0x00009a30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
|
||||
{ 0x00009a34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
|
||||
{ 0x00009a38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
|
||||
{ 0x00009a3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
|
||||
{ 0x00009a40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
|
||||
{ 0x00009a44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
|
||||
{ 0x00009a48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
|
||||
{ 0x00009a4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
|
||||
{ 0x00009a50, 0x00000000, 0x00000000, 0x00058220, 0x00058220, 0x00000000 },
|
||||
{ 0x00009a54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
|
||||
{ 0x00009a58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
|
||||
{ 0x00009a5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
|
||||
{ 0x00009a60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
|
||||
{ 0x00009a64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
|
||||
{ 0x00009a68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
|
||||
{ 0x00009a6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
|
||||
{ 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
|
||||
{ 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
|
||||
{ 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
|
||||
{ 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
|
||||
{ 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
|
||||
{ 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
|
||||
{ 0x00009a88, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000 },
|
||||
{ 0x00009a8c, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
|
||||
{ 0x00009a90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
|
||||
{ 0x00009a94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000 },
|
||||
{ 0x00009a98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000 },
|
||||
{ 0x00009a9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000 },
|
||||
{ 0x00009aa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000 },
|
||||
{ 0x00009aa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000 },
|
||||
{ 0x00009aa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000 },
|
||||
{ 0x00009aac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000 },
|
||||
{ 0x00009ab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000 },
|
||||
{ 0x00009ab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000 },
|
||||
{ 0x00009ab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000 },
|
||||
{ 0x00009abc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000 },
|
||||
{ 0x00009ac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000 },
|
||||
{ 0x00009ac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000 },
|
||||
{ 0x00009ac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000 },
|
||||
{ 0x00009acc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000 },
|
||||
{ 0x00009ad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000 },
|
||||
{ 0x00009ad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000 },
|
||||
{ 0x00009ad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000 },
|
||||
{ 0x00009adc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000 },
|
||||
{ 0x00009ae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000 },
|
||||
{ 0x00009ae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000 },
|
||||
{ 0x00009ae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000 },
|
||||
{ 0x00009aec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000 },
|
||||
{ 0x00009af0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000 },
|
||||
{ 0x00009af4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000 },
|
||||
{ 0x00009af8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000 },
|
||||
{ 0x00009afc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000 },
|
||||
{ 0x00009b00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000 },
|
||||
{ 0x00009b04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000 },
|
||||
{ 0x00009b08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000 },
|
||||
{ 0x00009b0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000 },
|
||||
{ 0x00009b10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000 },
|
||||
{ 0x00009b14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000 },
|
||||
{ 0x00009b18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000 },
|
||||
{ 0x00009b1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000 },
|
||||
{ 0x00009b20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000 },
|
||||
{ 0x00009b24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000 },
|
||||
{ 0x00009b28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000 },
|
||||
{ 0x00009b2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000 },
|
||||
{ 0x00009b30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000 },
|
||||
{ 0x00009b34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000 },
|
||||
{ 0x00009b38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000 },
|
||||
{ 0x00009b3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000 },
|
||||
{ 0x00009b40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000 },
|
||||
{ 0x00009b44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000 },
|
||||
{ 0x00009b48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000 },
|
||||
{ 0x00009b4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000 },
|
||||
{ 0x00009b50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000 },
|
||||
{ 0x00009b54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000 },
|
||||
{ 0x00009b58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000 },
|
||||
{ 0x00009b5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000 },
|
||||
{ 0x00009b60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000 },
|
||||
{ 0x00009b64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009ba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009ba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009ba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009be0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009be4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009be8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000aa00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
|
||||
{ 0x0000aa04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
|
||||
{ 0x0000aa08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
|
||||
{ 0x0000aa0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
|
||||
{ 0x0000aa10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
|
||||
{ 0x0000aa14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
|
||||
{ 0x0000aa18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
|
||||
{ 0x0000aa1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
|
||||
{ 0x0000aa20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
|
||||
{ 0x0000aa24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
|
||||
{ 0x0000aa28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
|
||||
{ 0x0000aa2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
|
||||
{ 0x0000aa30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
|
||||
{ 0x0000aa34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
|
||||
{ 0x0000aa38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
|
||||
{ 0x0000aa3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
|
||||
{ 0x0000aa40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
|
||||
{ 0x0000aa44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
|
||||
{ 0x0000aa48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
|
||||
{ 0x0000aa4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
|
||||
{ 0x0000aa50, 0x00000000, 0x00000000, 0x00058220, 0x00058220, 0x00000000 },
|
||||
{ 0x0000aa54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
|
||||
{ 0x0000aa58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
|
||||
{ 0x0000aa5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
|
||||
{ 0x0000aa60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
|
||||
{ 0x0000aa64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
|
||||
{ 0x0000aa68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
|
||||
{ 0x0000aa6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
|
||||
{ 0x0000aa70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
|
||||
{ 0x0000aa74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
|
||||
{ 0x0000aa78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
|
||||
{ 0x0000aa7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
|
||||
{ 0x0000aa80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
|
||||
{ 0x0000aa84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
|
||||
{ 0x0000aa88, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000 },
|
||||
{ 0x0000aa8c, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
|
||||
{ 0x0000aa90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
|
||||
{ 0x0000aa94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000 },
|
||||
{ 0x0000aa98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000 },
|
||||
{ 0x0000aa9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000 },
|
||||
{ 0x0000aaa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000 },
|
||||
{ 0x0000aaa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000 },
|
||||
{ 0x0000aaa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000 },
|
||||
{ 0x0000aaac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000 },
|
||||
{ 0x0000aab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000 },
|
||||
{ 0x0000aab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000 },
|
||||
{ 0x0000aab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000 },
|
||||
{ 0x0000aabc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000 },
|
||||
{ 0x0000aac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000 },
|
||||
{ 0x0000aac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000 },
|
||||
{ 0x0000aac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000 },
|
||||
{ 0x0000aacc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000 },
|
||||
{ 0x0000aad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000 },
|
||||
{ 0x0000aad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000 },
|
||||
{ 0x0000aad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000 },
|
||||
{ 0x0000aadc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000 },
|
||||
{ 0x0000aae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000 },
|
||||
{ 0x0000aae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000 },
|
||||
{ 0x0000aae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000 },
|
||||
{ 0x0000aaec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000 },
|
||||
{ 0x0000aaf0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000 },
|
||||
{ 0x0000aaf4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000 },
|
||||
{ 0x0000aaf8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000 },
|
||||
{ 0x0000aafc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000 },
|
||||
{ 0x0000ab00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000 },
|
||||
{ 0x0000ab04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000 },
|
||||
{ 0x0000ab08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000 },
|
||||
{ 0x0000ab0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000 },
|
||||
{ 0x0000ab10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000 },
|
||||
{ 0x0000ab14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000 },
|
||||
{ 0x0000ab18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000 },
|
||||
{ 0x0000ab1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000 },
|
||||
{ 0x0000ab20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000 },
|
||||
{ 0x0000ab24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000 },
|
||||
{ 0x0000ab28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000 },
|
||||
{ 0x0000ab2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000 },
|
||||
{ 0x0000ab30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000 },
|
||||
{ 0x0000ab34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000 },
|
||||
{ 0x0000ab38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000 },
|
||||
{ 0x0000ab3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000 },
|
||||
{ 0x0000ab40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000 },
|
||||
{ 0x0000ab44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000 },
|
||||
{ 0x0000ab48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000 },
|
||||
{ 0x0000ab4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000 },
|
||||
{ 0x0000ab50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000 },
|
||||
{ 0x0000ab54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000 },
|
||||
{ 0x0000ab58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000 },
|
||||
{ 0x0000ab5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000 },
|
||||
{ 0x0000ab60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000 },
|
||||
{ 0x0000ab64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000aba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000aba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000aba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abe0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abe4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abe8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
|
||||
{ 0x0000a20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
|
||||
{ 0x0000b20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
|
||||
{ 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
|
||||
{ 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
|
||||
{ 0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000, 0x0004a000 },
|
||||
{ 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
|
||||
};
|
||||
|
||||
static const u_int32_t ar9285Common_v2[][2] = {
|
||||
{ 0x0000000c, 0x00000000 },
|
||||
{ 0x00000030, 0x00020045 },
|
||||
{ 0x00000034, 0x00000005 },
|
||||
{ 0x00000040, 0x00000000 },
|
||||
{ 0x00000044, 0x00000008 },
|
||||
{ 0x00000048, 0x00000008 },
|
||||
{ 0x0000004c, 0x00000010 },
|
||||
{ 0x00000050, 0x00000000 },
|
||||
{ 0x00000054, 0x0000001f },
|
||||
{ 0x00000800, 0x00000000 },
|
||||
{ 0x00000804, 0x00000000 },
|
||||
{ 0x00000808, 0x00000000 },
|
||||
{ 0x0000080c, 0x00000000 },
|
||||
{ 0x00000810, 0x00000000 },
|
||||
{ 0x00000814, 0x00000000 },
|
||||
{ 0x00000818, 0x00000000 },
|
||||
{ 0x0000081c, 0x00000000 },
|
||||
{ 0x00000820, 0x00000000 },
|
||||
{ 0x00000824, 0x00000000 },
|
||||
{ 0x00001040, 0x002ffc0f },
|
||||
{ 0x00001044, 0x002ffc0f },
|
||||
{ 0x00001048, 0x002ffc0f },
|
||||
{ 0x0000104c, 0x002ffc0f },
|
||||
{ 0x00001050, 0x002ffc0f },
|
||||
{ 0x00001054, 0x002ffc0f },
|
||||
{ 0x00001058, 0x002ffc0f },
|
||||
{ 0x0000105c, 0x002ffc0f },
|
||||
{ 0x00001060, 0x002ffc0f },
|
||||
{ 0x00001064, 0x002ffc0f },
|
||||
{ 0x00001230, 0x00000000 },
|
||||
{ 0x00001270, 0x00000000 },
|
||||
{ 0x00001038, 0x00000000 },
|
||||
{ 0x00001078, 0x00000000 },
|
||||
{ 0x000010b8, 0x00000000 },
|
||||
{ 0x000010f8, 0x00000000 },
|
||||
{ 0x00001138, 0x00000000 },
|
||||
{ 0x00001178, 0x00000000 },
|
||||
{ 0x000011b8, 0x00000000 },
|
||||
{ 0x000011f8, 0x00000000 },
|
||||
{ 0x00001238, 0x00000000 },
|
||||
{ 0x00001278, 0x00000000 },
|
||||
{ 0x000012b8, 0x00000000 },
|
||||
{ 0x000012f8, 0x00000000 },
|
||||
{ 0x00001338, 0x00000000 },
|
||||
{ 0x00001378, 0x00000000 },
|
||||
{ 0x000013b8, 0x00000000 },
|
||||
{ 0x000013f8, 0x00000000 },
|
||||
{ 0x00001438, 0x00000000 },
|
||||
{ 0x00001478, 0x00000000 },
|
||||
{ 0x000014b8, 0x00000000 },
|
||||
{ 0x000014f8, 0x00000000 },
|
||||
{ 0x00001538, 0x00000000 },
|
||||
{ 0x00001578, 0x00000000 },
|
||||
{ 0x000015b8, 0x00000000 },
|
||||
{ 0x000015f8, 0x00000000 },
|
||||
{ 0x00001638, 0x00000000 },
|
||||
{ 0x00001678, 0x00000000 },
|
||||
{ 0x000016b8, 0x00000000 },
|
||||
{ 0x000016f8, 0x00000000 },
|
||||
{ 0x00001738, 0x00000000 },
|
||||
{ 0x00001778, 0x00000000 },
|
||||
{ 0x000017b8, 0x00000000 },
|
||||
{ 0x000017f8, 0x00000000 },
|
||||
{ 0x0000103c, 0x00000000 },
|
||||
{ 0x0000107c, 0x00000000 },
|
||||
{ 0x000010bc, 0x00000000 },
|
||||
{ 0x000010fc, 0x00000000 },
|
||||
{ 0x0000113c, 0x00000000 },
|
||||
{ 0x0000117c, 0x00000000 },
|
||||
{ 0x000011bc, 0x00000000 },
|
||||
{ 0x000011fc, 0x00000000 },
|
||||
{ 0x0000123c, 0x00000000 },
|
||||
{ 0x0000127c, 0x00000000 },
|
||||
{ 0x000012bc, 0x00000000 },
|
||||
{ 0x000012fc, 0x00000000 },
|
||||
{ 0x0000133c, 0x00000000 },
|
||||
{ 0x0000137c, 0x00000000 },
|
||||
{ 0x000013bc, 0x00000000 },
|
||||
{ 0x000013fc, 0x00000000 },
|
||||
{ 0x0000143c, 0x00000000 },
|
||||
{ 0x0000147c, 0x00000000 },
|
||||
{ 0x00004030, 0x00000002 },
|
||||
{ 0x0000403c, 0x00000002 },
|
||||
{ 0x00004024, 0x0000001f },
|
||||
{ 0x00004060, 0x00000000 },
|
||||
{ 0x00004064, 0x00000000 },
|
||||
{ 0x00007010, 0x00000031 },
|
||||
{ 0x00007034, 0x00000002 },
|
||||
{ 0x00007038, 0x000004c2 },
|
||||
{ 0x00008004, 0x00000000 },
|
||||
{ 0x00008008, 0x00000000 },
|
||||
{ 0x0000800c, 0x00000000 },
|
||||
{ 0x00008018, 0x00000700 },
|
||||
{ 0x00008020, 0x00000000 },
|
||||
{ 0x00008038, 0x00000000 },
|
||||
{ 0x0000803c, 0x00000000 },
|
||||
{ 0x00008048, 0x00000000 },
|
||||
{ 0x00008054, 0x00000000 },
|
||||
{ 0x00008058, 0x00000000 },
|
||||
{ 0x0000805c, 0x000fc78f },
|
||||
{ 0x00008060, 0x0000000f },
|
||||
{ 0x00008064, 0x00000000 },
|
||||
{ 0x00008070, 0x00000000 },
|
||||
{ 0x000080c0, 0x2a80001a },
|
||||
{ 0x000080c4, 0x05dc01e0 },
|
||||
{ 0x000080c8, 0x1f402710 },
|
||||
{ 0x000080cc, 0x01f40000 },
|
||||
{ 0x000080d0, 0x00001e00 },
|
||||
{ 0x000080d4, 0x00000000 },
|
||||
{ 0x000080d8, 0x00400000 },
|
||||
{ 0x000080e0, 0xffffffff },
|
||||
{ 0x000080e4, 0x0000ffff },
|
||||
{ 0x000080e8, 0x003f3f3f },
|
||||
{ 0x000080ec, 0x00000000 },
|
||||
{ 0x000080f0, 0x00000000 },
|
||||
{ 0x000080f4, 0x00000000 },
|
||||
{ 0x000080f8, 0x00000000 },
|
||||
{ 0x000080fc, 0x00020000 },
|
||||
{ 0x00008100, 0x00020000 },
|
||||
{ 0x00008104, 0x00000001 },
|
||||
{ 0x00008108, 0x00000052 },
|
||||
{ 0x0000810c, 0x00000000 },
|
||||
{ 0x00008110, 0x00000168 },
|
||||
{ 0x00008118, 0x000100aa },
|
||||
{ 0x0000811c, 0x00003210 },
|
||||
{ 0x00008120, 0x08f04810 },
|
||||
{ 0x00008124, 0x00000000 },
|
||||
{ 0x00008128, 0x00000000 },
|
||||
{ 0x0000812c, 0x00000000 },
|
||||
{ 0x00008130, 0x00000000 },
|
||||
{ 0x00008134, 0x00000000 },
|
||||
{ 0x00008138, 0x00000000 },
|
||||
{ 0x0000813c, 0x00000000 },
|
||||
{ 0x00008144, 0xffffffff },
|
||||
{ 0x00008168, 0x00000000 },
|
||||
{ 0x0000816c, 0x00000000 },
|
||||
{ 0x00008170, 0x32143320 },
|
||||
{ 0x00008174, 0xfaa4fa50 },
|
||||
{ 0x00008178, 0x00000100 },
|
||||
{ 0x0000817c, 0x00000000 },
|
||||
{ 0x000081c0, 0x00000000 },
|
||||
{ 0x000081d0, 0x0000320a },
|
||||
{ 0x000081ec, 0x00000000 },
|
||||
{ 0x000081f0, 0x00000000 },
|
||||
{ 0x000081f4, 0x00000000 },
|
||||
{ 0x000081f8, 0x00000000 },
|
||||
{ 0x000081fc, 0x00000000 },
|
||||
{ 0x00008200, 0x00000000 },
|
||||
{ 0x00008204, 0x00000000 },
|
||||
{ 0x00008208, 0x00000000 },
|
||||
{ 0x0000820c, 0x00000000 },
|
||||
{ 0x00008210, 0x00000000 },
|
||||
{ 0x00008214, 0x00000000 },
|
||||
{ 0x00008218, 0x00000000 },
|
||||
{ 0x0000821c, 0x00000000 },
|
||||
{ 0x00008220, 0x00000000 },
|
||||
{ 0x00008224, 0x00000000 },
|
||||
{ 0x00008228, 0x00000000 },
|
||||
{ 0x0000822c, 0x00000000 },
|
||||
{ 0x00008230, 0x00000000 },
|
||||
{ 0x00008234, 0x00000000 },
|
||||
{ 0x00008238, 0x00000000 },
|
||||
{ 0x0000823c, 0x00000000 },
|
||||
{ 0x00008240, 0x00100000 },
|
||||
{ 0x00008244, 0x0010f400 },
|
||||
{ 0x00008248, 0x00000100 },
|
||||
{ 0x0000824c, 0x0001e800 },
|
||||
{ 0x00008250, 0x00000000 },
|
||||
{ 0x00008254, 0x00000000 },
|
||||
{ 0x00008258, 0x00000000 },
|
||||
{ 0x0000825c, 0x400000ff },
|
||||
{ 0x00008260, 0x00080922 },
|
||||
{ 0x00008264, 0x88a00010 },
|
||||
{ 0x00008270, 0x00000000 },
|
||||
{ 0x00008274, 0x40000000 },
|
||||
{ 0x00008278, 0x003e4180 },
|
||||
{ 0x0000827c, 0x00000000 },
|
||||
{ 0x00008284, 0x0000002c },
|
||||
{ 0x00008288, 0x0000002c },
|
||||
{ 0x0000828c, 0x00000000 },
|
||||
{ 0x00008294, 0x00000000 },
|
||||
{ 0x00008298, 0x00000000 },
|
||||
{ 0x0000829c, 0x00000000 },
|
||||
{ 0x00008300, 0x00000040 },
|
||||
{ 0x00008314, 0x00000000 },
|
||||
{ 0x00008328, 0x00000000 },
|
||||
{ 0x0000832c, 0x00000001 },
|
||||
{ 0x00008330, 0x00000302 },
|
||||
{ 0x00008334, 0x00000e00 },
|
||||
{ 0x00008338, 0x00ff0000 },
|
||||
{ 0x0000833c, 0x00000000 },
|
||||
{ 0x00008340, 0x00010380 },
|
||||
{ 0x00008344, 0x00481043 },
|
||||
{ 0x00009808, 0x00000000 },
|
||||
{ 0x0000980c, 0xafe68e30 },
|
||||
{ 0x00009810, 0xfd14e000 },
|
||||
{ 0x00009814, 0x9c0a9f6b },
|
||||
{ 0x0000981c, 0x00000000 },
|
||||
{ 0x0000982c, 0x0000a000 },
|
||||
{ 0x00009830, 0x00000000 },
|
||||
{ 0x0000983c, 0x00200400 },
|
||||
{ 0x0000984c, 0x0040233c },
|
||||
{ 0x00009854, 0x00000044 },
|
||||
{ 0x00009900, 0x00000000 },
|
||||
{ 0x00009904, 0x00000000 },
|
||||
{ 0x00009908, 0x00000000 },
|
||||
{ 0x0000990c, 0x00000000 },
|
||||
{ 0x00009910, 0x01002310 },
|
||||
{ 0x0000991c, 0x10000fff },
|
||||
{ 0x00009920, 0x04900000 },
|
||||
{ 0x00009928, 0x00000001 },
|
||||
{ 0x0000992c, 0x00000004 },
|
||||
{ 0x00009934, 0x1e1f2022 },
|
||||
{ 0x00009938, 0x0a0b0c0d },
|
||||
{ 0x0000993c, 0x00000000 },
|
||||
{ 0x00009940, 0x14750604 },
|
||||
{ 0x00009948, 0x9280c00a },
|
||||
{ 0x0000994c, 0x00020028 },
|
||||
{ 0x00009954, 0x5f3ca3de },
|
||||
{ 0x00009958, 0x2108ecff },
|
||||
{ 0x00009968, 0x000003ce },
|
||||
{ 0x00009970, 0x192bb514 },
|
||||
{ 0x00009974, 0x00000000 },
|
||||
{ 0x00009978, 0x00000001 },
|
||||
{ 0x0000997c, 0x00000000 },
|
||||
{ 0x00009980, 0x00000000 },
|
||||
{ 0x00009984, 0x00000000 },
|
||||
{ 0x00009988, 0x00000000 },
|
||||
{ 0x0000998c, 0x00000000 },
|
||||
{ 0x00009990, 0x00000000 },
|
||||
{ 0x00009994, 0x00000000 },
|
||||
{ 0x00009998, 0x00000000 },
|
||||
{ 0x0000999c, 0x00000000 },
|
||||
{ 0x000099a0, 0x00000000 },
|
||||
{ 0x000099a4, 0x00000001 },
|
||||
{ 0x000099a8, 0x201fff00 },
|
||||
{ 0x000099ac, 0x2def0400 },
|
||||
{ 0x000099b0, 0x03051000 },
|
||||
{ 0x000099b4, 0x00000820 },
|
||||
{ 0x000099dc, 0x00000000 },
|
||||
{ 0x000099e0, 0x00000000 },
|
||||
{ 0x000099e4, 0xaaaaaaaa },
|
||||
{ 0x000099e8, 0x3c466478 },
|
||||
{ 0x000099ec, 0x0cc80caa },
|
||||
{ 0x000099f0, 0x00000000 },
|
||||
{ 0x0000a208, 0x803e68c8 },
|
||||
{ 0x0000a210, 0x4080a333 },
|
||||
{ 0x0000a214, 0x00206c10 },
|
||||
{ 0x0000a218, 0x009c4060 },
|
||||
{ 0x0000a220, 0x01834061 },
|
||||
{ 0x0000a224, 0x00000400 },
|
||||
{ 0x0000a228, 0x000003b5 },
|
||||
{ 0x0000a22c, 0x00000000 },
|
||||
{ 0x0000a234, 0x20202020 },
|
||||
{ 0x0000a238, 0x20202020 },
|
||||
{ 0x0000a244, 0x00000000 },
|
||||
{ 0x0000a248, 0xfffffffc },
|
||||
{ 0x0000a24c, 0x00000000 },
|
||||
{ 0x0000a254, 0x00000000 },
|
||||
{ 0x0000a258, 0x0ccb5380 },
|
||||
{ 0x0000a25c, 0x15151501 },
|
||||
{ 0x0000a260, 0xdfa90f01 },
|
||||
{ 0x0000a268, 0x00000000 },
|
||||
{ 0x0000a26c, 0x0ebae9e6 },
|
||||
{ 0x0000d270, 0x0d820820 },
|
||||
{ 0x0000d35c, 0x07ffffef },
|
||||
{ 0x0000d360, 0x0fffffe7 },
|
||||
{ 0x0000d364, 0x17ffffe5 },
|
||||
{ 0x0000d368, 0x1fffffe4 },
|
||||
{ 0x0000d36c, 0x37ffffe3 },
|
||||
{ 0x0000d370, 0x3fffffe3 },
|
||||
{ 0x0000d374, 0x57ffffe3 },
|
||||
{ 0x0000d378, 0x5fffffe2 },
|
||||
{ 0x0000d37c, 0x7fffffe2 },
|
||||
{ 0x0000d380, 0x7f3c7bba },
|
||||
{ 0x0000d384, 0xf3307ff0 },
|
||||
{ 0x0000a388, 0x0c000000 },
|
||||
{ 0x0000a38c, 0x20202020 },
|
||||
{ 0x0000a390, 0x20202020 },
|
||||
{ 0x0000a39c, 0x00000001 },
|
||||
{ 0x0000a3a0, 0x00000000 },
|
||||
{ 0x0000a3a4, 0x00000000 },
|
||||
{ 0x0000a3a8, 0x00000000 },
|
||||
{ 0x0000a3ac, 0x00000000 },
|
||||
{ 0x0000a3b0, 0x00000000 },
|
||||
{ 0x0000a3b4, 0x00000000 },
|
||||
{ 0x0000a3b8, 0x00000000 },
|
||||
{ 0x0000a3bc, 0x00000000 },
|
||||
{ 0x0000a3c0, 0x00000000 },
|
||||
{ 0x0000a3c4, 0x00000000 },
|
||||
{ 0x0000a3cc, 0x20202020 },
|
||||
{ 0x0000a3d0, 0x20202020 },
|
||||
{ 0x0000a3d4, 0x20202020 },
|
||||
{ 0x0000a3e4, 0x00000000 },
|
||||
{ 0x0000a3e8, 0x18c43433 },
|
||||
{ 0x0000a3ec, 0x00f70081 },
|
||||
{ 0x00007800, 0x00140000 },
|
||||
{ 0x00007804, 0x0e4548d8 },
|
||||
{ 0x00007808, 0x54214514 },
|
||||
{ 0x0000780c, 0x02025830 },
|
||||
{ 0x00007810, 0x71c0d388 },
|
||||
{ 0x00007814, 0x924934a8 },
|
||||
{ 0x0000781c, 0x00000000 },
|
||||
{ 0x00007824, 0x00d86fff },
|
||||
{ 0x00007828, 0x26d2491b },
|
||||
{ 0x0000782c, 0x6e36d97b },
|
||||
{ 0x00007830, 0xedb6d96e },
|
||||
{ 0x00007834, 0x71400087 },
|
||||
{ 0x0000783c, 0x0001fffe },
|
||||
{ 0x00007840, 0xffeb1a20 },
|
||||
{ 0x00007844, 0x000c0db6 },
|
||||
{ 0x00007848, 0x6db61b6f },
|
||||
{ 0x0000784c, 0x6d9b66db },
|
||||
{ 0x00007850, 0x6d8c6dba },
|
||||
{ 0x00007854, 0x00040000 },
|
||||
{ 0x00007858, 0xdb003012 },
|
||||
{ 0x0000785c, 0x04924914 },
|
||||
{ 0x00007860, 0x21084210 },
|
||||
{ 0x00007864, 0xf7d7ffde },
|
||||
{ 0x00007868, 0xc2034080 },
|
||||
{ 0x00007870, 0x10142c00 },
|
||||
};
|
||||
|
||||
static const u_int32_t ar9285Modes_high_power_tx_gain_v2[][6] = {
|
||||
/* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
|
||||
{ 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000 },
|
||||
{ 0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201, 0x00000000 },
|
||||
{ 0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240, 0x00000000 },
|
||||
{ 0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241, 0x00000000 },
|
||||
{ 0x0000a314, 0x00000000, 0x00000000, 0x0000f600, 0x0000f600, 0x00000000 },
|
||||
{ 0x0000a318, 0x00000000, 0x00000000, 0x00012800, 0x00012800, 0x00000000 },
|
||||
{ 0x0000a31c, 0x00000000, 0x00000000, 0x00016802, 0x00016802, 0x00000000 },
|
||||
{ 0x0000a320, 0x00000000, 0x00000000, 0x0001b805, 0x0001b805, 0x00000000 },
|
||||
{ 0x0000a324, 0x00000000, 0x00000000, 0x00021a80, 0x00021a80, 0x00000000 },
|
||||
{ 0x0000a328, 0x00000000, 0x00000000, 0x00028b00, 0x00028b00, 0x00000000 },
|
||||
{ 0x0000a32c, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40, 0x00000000 },
|
||||
{ 0x0000a330, 0x00000000, 0x00000000, 0x0002cd80, 0x0002cd80, 0x00000000 },
|
||||
{ 0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82, 0x00000000 },
|
||||
{ 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
|
||||
{ 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
|
||||
{ 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x00007838, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803 },
|
||||
{ 0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe },
|
||||
{ 0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00 },
|
||||
{ 0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a216652, 0x0a216652, 0x0a22a652 },
|
||||
{ 0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
|
||||
{ 0x0000a27c, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7 },
|
||||
{ 0x0000a394, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
|
||||
{ 0x0000a398, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
|
||||
{ 0x0000a3dc, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
|
||||
{ 0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
|
||||
};
|
||||
|
||||
static const u_int32_t ar9285Modes_original_tx_gain_v2[][6] = {
|
||||
/* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
|
||||
{ 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
|
||||
{ 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
|
||||
{ 0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000 },
|
||||
{ 0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618, 0x00000000 },
|
||||
{ 0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9, 0x00000000 },
|
||||
{ 0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710, 0x00000000 },
|
||||
{ 0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718, 0x00000000 },
|
||||
{ 0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758, 0x00000000 },
|
||||
{ 0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a, 0x00000000 },
|
||||
{ 0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c, 0x00000000 },
|
||||
{ 0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e, 0x00000000 },
|
||||
{ 0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f, 0x00000000 },
|
||||
{ 0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df, 0x00000000 },
|
||||
{ 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
|
||||
{ 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
|
||||
{ 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x00007838, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801 },
|
||||
{ 0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4 },
|
||||
{ 0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04 },
|
||||
{ 0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652, 0x0a22a652 },
|
||||
{ 0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
|
||||
{ 0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c },
|
||||
{ 0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
|
||||
{ 0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
|
||||
{ 0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
|
||||
{ 0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
|
||||
};
|
||||
|
||||
static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_v2[][2] = {
|
||||
{0x00004040, 0x9248fd00 },
|
||||
{0x00004040, 0x24924924 },
|
||||
{0x00004040, 0xa8000019 },
|
||||
{0x00004040, 0x13160820 },
|
||||
{0x00004040, 0xe5980560 },
|
||||
{0x00004040, 0xc01dcffd },
|
||||
{0x00004040, 0x1aaabe41 },
|
||||
{0x00004040, 0xbe105554 },
|
||||
{0x00004040, 0x00043007 },
|
||||
{0x00004044, 0x00000000 },
|
||||
};
|
||||
|
||||
static const u_int32_t ar9285PciePhy_clkreq_off_L1_v2[][2] = {
|
||||
{0x00004040, 0x9248fd00 },
|
||||
{0x00004040, 0x24924924 },
|
||||
{0x00004040, 0xa8000019 },
|
||||
{0x00004040, 0x13160820 },
|
||||
{0x00004040, 0xe5980560 },
|
||||
{0x00004040, 0xc01dcffc },
|
||||
{0x00004040, 0x1aaabe41 },
|
||||
{0x00004040, 0xbe105554 },
|
||||
{0x00004040, 0x00043007 },
|
||||
{0x00004044, 0x00000000 },
|
||||
};
|
||||
Loading…
x
Reference in New Issue
Block a user