Add a basic iomux driver for imx6.
Submitted by: bsam@
This commit is contained in:
Ian Lepore
parent
4734ecbfec
commit
f5a76413fe
@ -19,11 +19,12 @@ arm/arm/bus_space-v6.c standard
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arm/arm/mpcore_timer.c standard
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arm/freescale/fsl_ocotp.c standard
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arm/freescale/imx/imx6_anatop.c standard
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arm/freescale/imx/imx_common.c standard
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arm/freescale/imx/imx6_ccm.c standard
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arm/freescale/imx/imx6_iomux.c standard
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arm/freescale/imx/imx6_machdep.c standard
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arm/freescale/imx/imx6_mp.c optional smp
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arm/freescale/imx/imx6_pl310.c standard
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arm/freescale/imx/imx_common.c standard
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arm/freescale/imx/imx_machdep.c standard
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arm/freescale/imx/imx_gpt.c standard
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arm/freescale/imx/imx_gpio.c optional gpio
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189
sys/arm/freescale/imx/imx6_iomux.c
Normal file
189
sys/arm/freescale/imx/imx6_iomux.c
Normal file
@ -0,0 +1,189 @@
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/*-
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* Copyright (c) 2014 Boris Samorodov <bsam@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/fdt.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/freescale/imx/imx_iomuxvar.h>
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#include "imx6_iomuxreg.h"
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#define IOMUX_WRITE(_sc, _r, _v) \
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bus_write_4((_sc)->sc_res, (_r), (_v))
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#define IOMUX_READ(_sc, _r) \
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bus_read_4((_sc)->sc_res, (_r))
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#define IOMUX_SET(_sc, _r, _m) \
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IOMUX_WRITE((_sc), (_r), IOMUX_READ((_sc), (_r)) | (_m))
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#define IOMUX_CLEAR(_sc, _r, _m) \
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IOMUX_WRITE((_sc), (_r), IOMUX_READ((_sc), (_r)) & ~(_m))
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struct imx6_iomux_softc {
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struct resource *sc_res;
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device_t sc_dev;
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};
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static struct imx6_iomux_softc *iomuxsc = NULL;
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static struct resource_spec imx6_iomux_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static int
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imx6_iomux_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "fsl,imx6-iomux"))
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return (ENXIO);
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device_set_desc(dev, "Freescale i.MX6 IO pins multiplexor");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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imx6_iomux_attach(device_t dev)
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{
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struct imx6_iomux_softc * sc;
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sc = device_get_softc(dev);
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if (bus_alloc_resources(dev, imx6_iomux_spec, &sc->sc_res)) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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iomuxsc = sc;
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/*
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* XXX: place to fetch all info about pinmuxing from loader data
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* (FDT blob) and apply. Loader (1st one) must care about
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* device-to-device difference.
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*/
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return (0);
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}
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static int
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imx6_iomux_detach(device_t dev)
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{
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/* IOMUX registers are always accessible. */
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return (EBUSY);
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}
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static void
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iomux_set_pad_sub(struct imx6_iomux_softc *sc, uint32_t pin, uint32_t config)
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{
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bus_size_t pad_ctl_reg = IOMUX_PIN_TO_PAD_ADDRESS(pin);
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if (pad_ctl_reg != IOMUX_PAD_NONE)
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IOMUX_WRITE(sc, pad_ctl_reg, config);
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}
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void
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iomux_set_pad(unsigned int pin, unsigned int config)
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{
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if (iomuxsc == NULL)
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return;
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iomux_set_pad_sub(iomuxsc, pin, config);
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}
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static void
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iomux_set_function_sub(struct imx6_iomux_softc *sc, uint32_t pin, uint32_t fn)
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{
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bus_size_t mux_ctl_reg = IOMUX_PIN_TO_MUX_ADDRESS(pin);
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if (mux_ctl_reg != IOMUX_MUX_NONE)
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IOMUX_WRITE(sc, mux_ctl_reg, fn);
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}
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void
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iomux_set_function(unsigned int pin, unsigned int fn)
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{
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if (iomuxsc == NULL)
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return;
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iomux_set_function_sub(iomuxsc, pin, fn);
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}
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static uint32_t
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iomux_get_pad_config_sub(struct imx6_iomux_softc *sc, uint32_t pin)
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{
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bus_size_t pad_reg = IOMUX_PIN_TO_PAD_ADDRESS(pin);
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uint32_t result;
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result = IOMUX_READ(sc, pad_reg);
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return(result);
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}
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unsigned int
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iomux_get_pad_config(unsigned int pin)
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{
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return(iomux_get_pad_config_sub(iomuxsc, pin));
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}
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static device_method_t imx6_iomux_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, imx6_iomux_probe),
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DEVMETHOD(device_attach, imx6_iomux_attach),
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DEVMETHOD(device_detach, imx6_iomux_detach),
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DEVMETHOD_END
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};
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static driver_t imx6_iomux_driver = {
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"imx6_iomux",
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imx6_iomux_methods,
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sizeof(struct imx6_iomux_softc),
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};
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static devclass_t imx6_iomux_devclass;
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EARLY_DRIVER_MODULE(imx6_iomux, simplebus, imx6_iomux_driver,
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imx6_iomux_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_LATE);
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798
sys/arm/freescale/imx/imx6_iomuxreg.h
Normal file
798
sys/arm/freescale/imx/imx6_iomuxreg.h
Normal file
@ -0,0 +1,798 @@
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/*-
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* Copyright (c) 2014 Boris Samorodov <bsam@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Pad : pin ("pin" is used at electric schemes,
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* while at HW SOC it's named "pad").
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* Drive strength : the current that can be drawn with
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* appropriate voltage (varies inversely with
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* the supply impedance of the output pin).
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* Drive strength enable (DSE) : The value of the current the pin uses.
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* HiZ (HYZ) : high input impedance value.
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* Daisy chain (DAISY) : the one after another interconnection of
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* devices.
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* On die termination (ODT) : the termination resistor for impedance
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* matching.
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* Software input on (SION) : the value to force the pin to be an input
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* one (i.e. to force the pin state reading).
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* Hysteresis (HYS) : Controls if the value of the input pin
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* remains the same until a sufficient change
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* is applied.
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* Slow rate enable (SRE) : How slow the pin value changes (slow rate
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* saves power).
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* Open drain enable (ODE) : If the input pin drains on low input or
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* goes down.
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* Pull/keep enable (PKE) : Enables pull/keep functionality.
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* PUll/keep select (PUE) : Selects if the pin is pullup/pulldown one
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* or remains it's previous role.
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* A note: I'm not sure why it's not PKS...
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* Pullup (Pic.1)/pulldown (Pic.2): the pin's resistor connected to VCC (GND)
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* to prevent random value drai.
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* Pullup/pulldown select (PUS) : Selects the value of pullup/pulldown
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* resistor.
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* Open drain (Pic.3) : the output signal is applied to the base
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* of a transistor whose collector is used
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* as a pin.
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*
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* VCC o VCC o Open drain
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* | | ----> pin
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* +++ o| /
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* | | R | Switch /
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* +++ pullup o| .---.
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* | | / |/ \
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* >---+------> Pin >---+------> Pin >---{--| )
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* | | \ |\ /
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* o| +++ `--v'
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* | Switch | | R \
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* o| +++ pulldown |
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* | | |
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* ----- ----- -----
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* --- --- ---
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* - - -
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*
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* Pic.1 Pic.2 Pic.3
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*/
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#ifndef IMX6_IOMUXREG_H
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#define IMX6_IOMUXREG_H
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/*
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* Multiplex control
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*/
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#define IOMUXC_MUX_CTL 0x004c
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#define IOMUX_CONFIG_SION (1<<4)
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#define IOMUX_CONFIG_ALT0 0
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#define IOMUX_CONFIG_ALT1 1
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#define IOMUX_CONFIG_ALT2 2
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#define IOMUX_CONFIG_ALT3 3
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#define IOMUX_CONFIG_ALT4 4
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#define IOMUX_CONFIG_ALT5 5
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#define IOMUX_CONFIG_ALT6 6
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#define IOMUX_CONFIG_ALT7 7
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/*
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* Pad control
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*/
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#define IOMUXC_PAD_CTL 0x0360
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/* DDR Select Field */
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#define PAD_CTL_DDR_SEL_0 (0x0<<18)
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#define PAD_CTL_DDR_SEL_1 (0x1<<18)
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#define PAD_CTL_DDR_SEL_2 (0x2<<18)
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#define PAD_CTL_DDR_SEL_3 (0x3<<18)
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#define PAD_CTL_DDR_INPUT (0x1<<17) /* DDR/CMOS Input Mode Field */
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#define PAD_CTL_HYS (1<<16) /* Hysteresis Enable Field */
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/* PullUp/Down Config Field: */
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#define PAD_CTL_PUS_100K_PD (0x0<<14) /* 100K Ohm Pull Down */
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#define PAD_CTL_PUS_47K_PU (0x1<<14) /* 47K Ohn Pull Up */
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#define PAD_CTL_PUS_100K_PU (0x2<<14) /* 100K Ohm Pull Up */
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#define PAD_CTL_PUS_22K_PU (0x3<<14) /* 22K Ohm Pull Up */
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#define PAD_CTL_PUE (1<<13) /* Pull/Keep Select Field */
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#define PAD_CTL_PKE (1<<12) /* Pull/Keep Enable Field */
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#define PAD_CTL_ODE (1<<11) /* Open Drain Enable Field */
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/* On Die Termination Field: */
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#define PAD_CTL_ODT_DISABLED (0x0<<8) /* Disabled */
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#define PAD_CTL_ODT_1 (0x1<<8)
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#define PAD_CTL_ODT_2 (0x2<<8)
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#define PAD_CTL_ODT_3 (0x3<<8)
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#define PAD_CTL_ODT_4 (0x4<<8)
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#define PAD_CTL_ODT_5 (0x5<<8)
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#define PAD_CTL_ODT_6 (0x6<<8)
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#define PAD_CTL_ODT_7 (0x7<<8)
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/* Speed Field: */
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#define PAD_CTL_SPEED_RESERVED0 (0x0<<6) /* RESERVED */
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#define PAD_CTL_SPEED_50_MHZ (0x1<<6) /* 50 MHz */
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#define PAD_CTL_SPEED_100_MHZ (0x2<<6) /* 100 MHz */
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#define PAD_CTL_SPEED_200_MHZ (0x3<<6) /* 200 MHz */
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/* Drive Strength Field */
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#define PAD_CTL_DSE_HIZ (0x0<<3) /* HI-Z */
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#define PAD_CTL_DSE_1 (0x1<<3)
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#define PAD_CTL_DSE_2 (0x2<<3)
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#define PAD_CTL_DSE_3 (0x3<<3)
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#define PAD_CTL_DSE_4 (0x4<<3)
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#define PAD_CTL_DSE_5 (0x5<<3)
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#define PAD_CTL_DSE_6 (0x6<<3)
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#define PAD_CTL_DSE_7 (0x7<<3)
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#define PAD_CTL_SRE (0x1<<0) /* Slew rate Field */
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/*
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* Input control
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*/
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#define IOMUXC_INPUT_CTL 0x07b0 /* input control */
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#define INPUT_DAISY_0 0
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#define INPUT_DAISY_1 1
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#define INPUT_DAISY_2 2
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#define INPUT_DAISY_3 3
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#define INPUT_DAISY_4 4
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#define INPUT_DAISY_5 5
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#define INPUT_DAISY_6 6
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#define INPUT_DAISY_7 7
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/*
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* IOMUX index
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*/
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#define IOMUX_PIN_TO_MUX_ADDRESS(pin) (((pin) >> 16) & 0xffff)
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#define IOMUX_PIN_TO_PAD_ADDRESS(pin) (((pin) >> 0) & 0xffff)
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#define IOMUX_PIN(mux_adr, pad_adr) \
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(((mux_adr) << 16) | (((pad_adr) << 0)))
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#define IOMUX_MUX_NONE 0xffff
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#define IOMUX_PAD_NONE 0xffff
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/*
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* MUX & PAD Control
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*/
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#define MUX_PIN(name) \
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IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_##name, \
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IOMUXC_SW_PAD_CTL_PAD_##name)
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#define MUX_PIN_MUX(name) \
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IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_##name, IOMUX_PAD_NONE)
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#define MUX_PIN_PAD(name) \
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IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_##name)
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#define MUX_PIN_GRP(name) \
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IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_GRP_##name)
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#define MUX_PIN_PATH(name) \
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IOMUX_PIN(IOMUXC_##name##_SELECT_INPUT, IOMUX_MUX_NONE)
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/*
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* INPUT Control
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*/
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#define MUX_SELECT(name) (name##_SELECT_INPUT)
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/*
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* Register names, offset addresses (and reset values for reference)
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* from Chapter 36 IOMUX Controller (IOMUXC), IMX6DQRM, Rev.1, 04/2013
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*
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* General Purpose Registers
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*/
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#define IOMUXC_GPR0 0x0000 /* 0x00000000 */
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#define IOMUXC_GPR1 0x0004 /* 0x48400005 */
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#define IOMUXC_GPR2 0x0008 /* 0x00000000 */
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#define IOMUXC_GPR3 0x000c /* 0x01e00000 */
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#define IOMUXC_GPR4 0x0010 /* 0x00000000 */
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#define IOMUXC_GPR5 0x0014 /* 0x00000000 */
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#define IOMUXC_GPR6 0x0018 /* 0x22222222 */
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#define IOMUXC_GPR7 0x001c /* 0x22222222 */
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#define IOMUXC_GPR8 0x0020 /* 0x00000000 */
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#define IOMUXC_GPR9 0x0024 /* 0x00000000 */
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#define IOMUXC_GPR10 0x0028 /* 0x00003800 */
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#define IOMUXC_GPR11 0x002c /* 0x00003800 */
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#define IOMUXC_GPR12 0x0030 /* 0x0f000000 */
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#define IOMUXC_GPR13 0x0034 /* 0x059124c4 */
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||||
/*
|
||||
* Pad Mux Registers
|
||||
*/
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 0x004c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 0x0050 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 0x0054 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC 0x0058 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0 0x005c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1 0x0060 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2 0x0064 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3 0x0068 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL 0x006c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0 0x0070 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL 0x0074 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1 0x0078 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2 0x007c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3 0x0080 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC 0x0084 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25 0x0088 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_B 0x008c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16 0x0090 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17 0x0094 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18 0x0098 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19 0x009c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 0x00a0 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x00a4 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22 0x00a8 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23 0x00ac /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_B 0x00b0 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24 0x00b4 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25 0x00b8 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26 0x00bc /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27 0x00c0 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x00c4 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29 0x00c8 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30 0x00cc /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31 0x00d0 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24 0x00d4 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23 0x00d8 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22 0x00dc /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21 0x00e0 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20 0x00e4 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19 0x00e8 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18 0x00ec /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17 0x00f0 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16 0x00f4 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B 0x00f8 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_B 0x00fc /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B 0x0100 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_RW 0x0104 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B 0x0108 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_B 0x010c /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_B 0x0110 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD00 0x0114 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD01 0x0118 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD02 0x011c /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD03 0x0120 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD04 0x0124 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD05 0x0128 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD06 0x012c /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD07 0x0130 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD08 0x0134 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD09 0x0138 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD10 0x013c /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD11 0x0140 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD12 0x0144 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD13 0x0148 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD14 0x014c /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD15 0x0150 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B 0x0154 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK 0x0158 /* 0x00000000 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK 0x015c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15 0x0160 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02 0x0164 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03 0x0168 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04 0x016c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00 0x0170 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01 0x0174 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02 0x0178 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03 0x017c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04 0x0180 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05 0x0184 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06 0x0188 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07 0x018c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08 0x0190 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09 0x0194 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10 0x0198 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11 0x019c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12 0x01a0 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13 0x01a4 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14 0x01a8 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15 0x01ac /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16 0x01b0 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17 0x01b4 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18 0x01b8 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19 0x01bc /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20 0x01c0 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21 0x01c4 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22 0x01c8 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23 0x01cc /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO 0x01d0 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK 0x01d4 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER 0x01d8 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV 0x01dc /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1 0x01e0 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0 0x01e4 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN 0x01e8 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1 0x01ec /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0 0x01f0 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_ENET_MDC 0x01f4 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 0x01f8 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 0x01fc /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 0x0200 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 0x0204 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 0x0208 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 0x020c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 0x0210 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 0x0214 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 0x0218 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4 0x021c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_GPIO00 0x0220 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_GPIO01 0x0224 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_GPIO09 0x0228 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_GPIO03 0x022c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_GPIO06 0x0230 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_GPIO02 0x0234 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_GPIO04 0x0238 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_GPIO05 0x023c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_GPIO07 0x0240 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_GPIO08 0x0244 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_GPIO16 0x0248 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x024c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_GPIO18 0x0250 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_GPIO19 0x0254 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK 0x0258 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC 0x025c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN 0x0260 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC 0x0264 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04 0x0268 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05 0x026c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06 0x0270 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07 0x0274 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08 0x0278 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09 0x027c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10 0x0280 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11 0x0284 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12 0x0288 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13 0x028c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14 0x0290 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15 0x0294 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16 0x0298 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17 0x029c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18 0x02a0 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19 0x02a4 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x02a8 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 0x02ac /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5 0x02b0 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4 0x02b4 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD 0x02b8 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK 0x02bc /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 0x02c0 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 0x02c4 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2 0x02c8 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3 0x02cc /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET 0x02d0 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x02d4 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x02d8 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x02dc /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B 0x02e0 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B 0x02e4 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B 0x02e8 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B 0x02ec /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B 0x02f0 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD 0x02f4 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK 0x02f8 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 0x02fc /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 0x0300 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 0x0304 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 0x0308 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 0x030c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x0310 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x0314 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x0318 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0 0x031c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1 0x0320 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2 0x0324 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3 0x0328 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4 0x032c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5 0x0330 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6 0x0334 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7 0x0338 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 0x033c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 0x0340 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 0x0344 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD 0x0348 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 0x034c /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK 0x0350 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK 0x0354 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD 0x0358 /* 0x00000005 */
|
||||
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 0x035c /* 0x00000005 */
|
||||
/*
|
||||
* Pad Control registers
|
||||
*/
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 0x0360 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 0x0364 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 0x0368 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC 0x036c /* 0x00013030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0 0x0370 /* 0x0001b030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1 0x0374 /* 0x0001b030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2 0x0378 /* 0x0001b030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3 0x037c /* 0x0001b030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL 0x0380 /* 0x00013030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0 0x0384 /* 0x0001b030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL 0x0388 /* 0x00013030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1 0x038c /* 0x0001b030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2 0x0390 /* 0x0001b030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3 0x0394 /* 0x0001b030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC 0x0398 /* 0x00013030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25 0x039c /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_B 0x03a0 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16 0x03a4 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17 0x03a8 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18 0x03ac /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19 0x03b0 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20 0x03b4 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x03b8 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22 0x03bc /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23 0x03c0 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_B 0x03c4 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24 0x03c8 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25 0x03cc /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26 0x03d0 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27 0x03d4 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x03d8 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29 0x03dc /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30 0x03e0 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31 0x03e4 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24 0x03e8 /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23 0x03ec /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22 0x03f0 /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21 0x03f4 /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20 0x03f8 /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19 0x03fc /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18 0x0400 /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17 0x0404 /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16 0x0408 /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_B 0x040c /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_B 0x0410 /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_OE_B 0x0414 /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_RW 0x0418 /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_B 0x041c /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_B 0x0420 /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_B 0x0424 /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD00 0x0428 /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD01 0x042c /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD02 0x0430 /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD03 0x0434 /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD04 0x0438 /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD05 0x043c /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD06 0x0440 /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD07 0x0444 /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD08 0x0448 /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD09 0x044c /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD10 0x0450 /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD11 0x0454 /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD12 0x0458 /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD13 0x045c /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD14 0x0460 /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD15 0x0464 /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_B 0x0468 /* 0x0000b060 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK 0x046c /* 0x0000b0b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK 0x0470 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15 0x0474 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02 0x0478 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03 0x047c /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04 0x0480 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00 0x0484 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01 0x0488 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02 0x048c /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03 0x0490 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04 0x0494 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05 0x0498 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06 0x049c /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07 0x04a0 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08 0x04a4 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09 0x04a8 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10 0x04ac /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11 0x04b0 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12 0x04b4 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13 0x04b8 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14 0x04bc /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15 0x04c0 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16 0x04c4 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17 0x04c8 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18 0x04cc /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19 0x04d0 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20 0x04d4 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21 0x04d8 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22 0x04dc /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23 0x04e0 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO 0x04e4 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK 0x04e8 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER 0x04ec /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV 0x04f0 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1 0x04f4 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0 0x04f8 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN 0x04fc /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1 0x0500 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0 0x0504 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_ENET_MDC 0x0508 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P 0x050c /* 0x00002030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 0x0510 /* 0x00008030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 0x0514 /* 0x00008030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P 0x0518 /* 0x00002030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P 0x051c /* 0x00002030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x0520 /* 0x00008030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P 0x0524 /* 0x00002030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x0528 /* 0x00008030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 0x052c /* 0x00008000 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 0x0530 /* 0x00008000 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 0x0534 /* 0x00008000 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 0x0538 /* 0x00008000 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 0x053c /* 0x00008000 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 0x0540 /* 0x00008000 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 0x0544 /* 0x00008000 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 0x0548 /* 0x00008000 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 0x054c /* 0x00008000 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 0x0550 /* 0x00008000 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 0x0554 /* 0x00008000 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 0x0558 /* 0x00008000 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 0x055c /* 0x00008000 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 0x0560 /* 0x00008000 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 0x0564 /* 0x00008000 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 0x0568 /* 0x00008000 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B 0x056c /* 0x00008030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B 0x0570 /* 0x00008000 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B 0x0574 /* 0x00008000 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B 0x0578 /* 0x00008030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 0x057c /* 0x00083030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 0x0580 /* 0x00008000 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 0x0584 /* 0x00008000 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P 0x0588 /* 0x00008030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 0x058c /* 0x0000b000 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x0590 /* 0x00003000 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P 0x0594 /* 0x00008030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x0598 /* 0x00003000 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 0x059c /* 0x00003030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 0x05a0 /* 0x00003030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B 0x05a4 /* 0x00008000 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P 0x05a8 /* 0x00002030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x05ac /* 0x00008030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P 0x05b0 /* 0x00002030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x05b4 /* 0x00008030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P 0x05b8 /* 0x00002030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 0x05bc /* 0x00008030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P 0x05c0 /* 0x00002030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 0x05c4 /* 0x00008030 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 0x05c8 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 0x05cc /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 0x05d0 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 0x05d4 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 0x05d8 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 0x05dc /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 0x05e0 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 0x05e4 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 0x05e8 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4 0x05ec /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_GPIO00 0x05f0 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_GPIO01 0x05f4 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_GPIO09 0x05f8 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_GPIO03 0x05fc /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_GPIO06 0x0600 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_GPIO02 0x0604 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_GPIO04 0x0608 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_GPIO05 0x060c /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_GPIO07 0x0610 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_GPIO08 0x0614 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_GPIO16 0x0618 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_GPIO17 0x061c /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_GPIO18 0x0620 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_GPIO19 0x0624 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK 0x0628 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC 0x062c /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN 0x0630 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC 0x0634 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04 0x0638 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05 0x063c /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06 0x0640 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07 0x0644 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08 0x0648 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09 0x064c /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10 0x0650 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11 0x0654 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12 0x0658 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13 0x065c /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14 0x0660 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15 0x0664 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16 0x0668 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17 0x066c /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18 0x0670 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19 0x0674 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS 0x0678 /* 0x00007060 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD 0x067c /* 0x0000b060 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB 0x0680 /* 0x00007060 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI 0x0684 /* 0x00007060 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK 0x0688 /* 0x00007060 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO 0x068c /* 0x000090b1 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7 0x0690 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6 0x0694 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5 0x0698 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4 0x069c /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD 0x06a0 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK 0x06a4 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0 0x06a8 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1 0x06ac /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2 0x06b0 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3 0x06b4 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET 0x06b8 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE 0x06bc /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE 0x06c0 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B 0x06c4 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B 0x06c8 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B 0x06cc /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B 0x06d0 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B 0x06d4 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B 0x06d8 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD 0x06dc /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK 0x06e0 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 0x06e4 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 0x06e8 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 0x06ec /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 0x06f0 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 0x06f4 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 0x06f8 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 0x06fc /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 0x0700 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0 0x0704 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1 0x0708 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2 0x070c /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3 0x0710 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4 0x0714 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5 0x0718 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6 0x071c /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7 0x0720 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 0x0724 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 0x0728 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 0x072c /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD 0x0730 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 0x0734 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK 0x0738 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK 0x073c /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD 0x0740 /* 0x0001b0b0 */
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 0x0744 /* 0x0001b0b0 */
|
||||
/*
|
||||
* Pad Group Control Registers
|
||||
*/
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_B7DS 0x0748 /* 0x00000030 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x074c /* 0x00000030 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x0750 /* 0x00000000 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0 0x0754 /* 0x00000000 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x0758 /* 0x00001000 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1 0x075c /* 0x00000000 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2 0x0760 /* 0x00000000 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3 0x0764 /* 0x00000000 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x0768 /* 0x00002000 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4 0x076c /* 0x00000000 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x0770 /* 0x00000000 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x0774 /* 0x00000000 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5 0x0778 /* 0x00000000 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6 0x077c /* 0x00000000 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7 0x0780 /* 0x00000000 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x0784 /* 0x00000030 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x0788 /* 0x00000030 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x078c /* 0x00000030 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII 0x0790 /* 0x00080000 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_B2DS 0x0794 /* 0x00000030 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x0798 /* 0x00080000 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_B3DS 0x079c /* 0x00000030 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_B4DS 0x07a0 /* 0x00000030 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_B5DS 0x07a4 /* 0x00000030 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_B6DS 0x07a8 /* 0x00000030 */
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM 0x07ac /* 0x00000000 */
|
||||
/*
|
||||
* Select Input Registers
|
||||
*/
|
||||
#define IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT 0x07b0 /* 0x00000000 */
|
||||
#define IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT 0x07b4 /* 0x00000000 */
|
||||
#define IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT 0x07b8 /* 0x00000000 */
|
||||
#define IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT 0x07bc /* 0x00000000 */
|
||||
#define IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT 0x07c0 /* 0x00000000 */
|
||||
#define IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT 0x07c4 /* 0x00000000 */
|
||||
#define IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT 0x07c8 /* 0x00000000 */
|
||||
#define IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT 0x07cc /* 0x00000000 */
|
||||
#define IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT 0x07d0 /* 0x00000000 */
|
||||
#define IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT 0x07d4 /* 0x00000000 */
|
||||
#define IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT 0x07d8 /* 0x00000000 */
|
||||
#define IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT 0x07dc /* 0x00000000 */
|
||||
#define IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT 0x07e0 /* 0x00000000 */
|
||||
#define IOMUXC_FLEXCAN1_RX_SELECT_INPUT 0x07e4 /* 0x00000000 */
|
||||
#define IOMUXC_FLEXCAN2_RX_SELECT_INPUT 0x07e8 /* 0x00000000 */
|
||||
#define IOMUXC_CCM_PMIC_READY_SELECT_INPUT 0x07f0 /* 0x00000000 */
|
||||
#define IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT 0x07f4 /* 0x00000000 */
|
||||
#define IOMUXC_ECSPI1_MISO_SELECT_INPUT 0x07f8 /* 0x00000000 */
|
||||
#define IOMUXC_ECSPI1_MOSI_SELECT_INPUT 0x07fc /* 0x00000000 */
|
||||
#define IOMUXC_ECSPI1_SS0_SELECT_INPUT 0x0800 /* 0x00000000 */
|
||||
#define IOMUXC_ECSPI1_SS1_SELECT_INPUT 0x0804 /* 0x00000000 */
|
||||
#define IOMUXC_ECSPI1_SS2_SELECT_INPUT 0x0808 /* 0x00000000 */
|
||||
#define IOMUXC_ECSPI1_SS3_SELECT_INPUT 0x080c /* 0x00000000 */
|
||||
#define IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT 0x0810 /* 0x00000000 */
|
||||
#define IOMUXC_ECSPI2_MISO_SELECT_INPUT 0x0814 /* 0x00000000 */
|
||||
#define IOMUXC_ECSPI2_MOSI_SELECT_INPUT 0x0818 /* 0x00000000 */
|
||||
#define IOMUXC_ECSPI2_SS0_SELECT_INPUT 0x081c /* 0x00000000 */
|
||||
#define IOMUXC_ECSPI2_SS1_SELECT_INPUT 0x0820 /* 0x00000000 */
|
||||
#define IOMUXC_ECSPI4_SS0_SELECT_INPUT 0x0824 /* 0x00000000 */
|
||||
#define IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT 0x0828 /* 0x00000000 */
|
||||
#define IOMUXC_ECSPI5_MISO_SELECT_INPUT 0x082c /* 0x00000000 */
|
||||
#define IOMUXC_ECSPI5_MOSI_SELECT_INPUT 0x0830 /* 0x00000000 */
|
||||
#define IOMUXC_ECSPI5_SS0_SELECT_INPUT 0x0834 /* 0x00000000 */
|
||||
#define IOMUXC_ECSPI5_SS1_SELECT_INPUT 0x0838 /* 0x00000000 */
|
||||
#define IOMUXC_ENET_REF_CLK_SELECT_INPUT 0x083c /* 0x00000000 */
|
||||
#define IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT 0x0840 /* 0x00000000 */
|
||||
#define IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT 0x0844 /* 0x00000000 */
|
||||
#define IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT 0x0848 /* 0x00000000 */
|
||||
#define IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT 0x084c /* 0x00000000 */
|
||||
#define IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT 0x0850 /* 0x00000000 */
|
||||
#define IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT 0x0854 /* 0x00000000 */
|
||||
#define IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT 0x0858 /* 0x00000000 */
|
||||
#define IOMUXC_ESAI_RX_FS_SELECT_INPUT 0x085c /* 0x00000000 */
|
||||
#define IOMUXC_ESAI_TX_FS_SELECT_INPUT 0x0860 /* 0x00000000 */
|
||||
#define IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT 0x0864 /* 0x00000000 */
|
||||
#define IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT 0x0868 /* 0x00000000 */
|
||||
#define IOMUXC_ESAI_RX_CLK_SELECT_INPUT 0x086c /* 0x00000000 */
|
||||
#define IOMUXC_ESAI_TX_CLK_SELECT_INPUT 0x0870 /* 0x00000000 */
|
||||
#define IOMUXC_ESAI_SDO0_SELECT_INPUT 0x0874 /* 0x00000000 */
|
||||
#define IOMUXC_ESAI_SDO1_SELECT_INPUT 0x0878 /* 0x00000000 */
|
||||
#define IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT 0x087c /* 0x00000000 */
|
||||
#define IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT 0x0880 /* 0x00000000 */
|
||||
#define IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT 0x0884 /* 0x00000000 */
|
||||
#define IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT 0x0888 /* 0x00000000 */
|
||||
#define IOMUXC_HDMI_ICECIN_SELECT_INPUT 0x088c /* 0x00000000 */
|
||||
#define IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT 0x0890 /* 0x00000000 */
|
||||
#define IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT 0x0894 /* 0x00000000 */
|
||||
#define IOMUXC_I2C1_SCL_IN_SELECT_INPUT 0x0898 /* 0x00000000 */
|
||||
#define IOMUXC_I2C1_SDA_IN_SELECT_INPUT 0x089c /* 0x00000000 */
|
||||
#define IOMUXC_I2C2_SCL_IN_SELECT_INPUT 0x08a0 /* 0x00000000 */
|
||||
#define IOMUXC_I2C2_SDA_IN_SELECT_INPUT 0x08a4 /* 0x00000000 */
|
||||
#define IOMUXC_I2C3_SCL_IN_SELECT_INPUT 0x08a8 /* 0x00000000 */
|
||||
#define IOMUXC_I2C3_SDA_IN_SELECT_INPUT 0x08ac /* 0x00000000 */
|
||||
#define IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT 0x08b0 /* 0x00000000 */
|
||||
#define IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT 0x08b4 /* 0x00000000 */
|
||||
#define IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT 0x08b8 /* 0x00000000 */
|
||||
#define IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT 0x08bc /* 0x00000000 */
|
||||
#define IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT 0x08c0 /* 0x00000000 */
|
||||
#define IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT 0x08c4 /* 0x00000000 */
|
||||
#define IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT 0x08c8 /* 0x00000000 */
|
||||
#define IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT 0x08cc /* 0x00000000 */
|
||||
#define IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT 0x08d0 /* 0x00000000 */
|
||||
#define IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT 0x08d4 /* 0x00000000 */
|
||||
#define IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT 0x08d8 /* 0x00000000 */
|
||||
#define IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT 0x08dc /* 0x00000000 */
|
||||
#define IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT 0x08e0 /* 0x00000000 */
|
||||
#define IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT 0x08e4 /* 0x00000000 */
|
||||
#define IOMUXC_KEY_COL5_SELECT_INPUT 0x08e8 /* 0x00000000 */
|
||||
#define IOMUXC_KEY_COL6_SELECT_INPUT 0x08ec /* 0x00000000 */
|
||||
#define IOMUXC_KEY_COL7_SELECT_INPUT 0x08f0 /* 0x00000000 */
|
||||
#define IOMUXC_KEY_ROW5_SELECT_INPUT 0x08f4 /* 0x00000000 */
|
||||
#define IOMUXC_KEY_ROW6_SELECT_INPUT 0x08f8 /* 0x00000000 */
|
||||
#define IOMUXC_KEY_ROW7_SELECT_INPUT 0x08fc /* 0x00000000 */
|
||||
#define IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT 0x0900 /* 0x00000000 */
|
||||
#define IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT 0x0904 /* 0x00000000 */
|
||||
#define IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT 0x0908 /* 0x00000000 */
|
||||
#define IOMUXC_SDMA_EVENTS14_SELECT_INPUT 0x090c /* 0x00000000 */
|
||||
#define IOMUXC_SDMA_EVENTS15_SELECT_INPUT 0x0910 /* 0x00000000 */
|
||||
#define IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT 0x0914 /* 0x00000000 */
|
||||
#define IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT 0x0918 /* 0x00000000 */
|
||||
#define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x091c /* 0x00000000 */
|
||||
#define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x0920 /* 0x00000000 */
|
||||
#define IOMUXC_UART2_UART_RTS_B_SELECT_INPUT 0x0924 /* 0x00000000 */
|
||||
#define IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT 0x0928 /* 0x00000000 */
|
||||
#define IOMUXC_UART3_UART_RTS_B_SELECT_INPUT 0x092c /* 0x00000000 */
|
||||
#define IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT 0x0930 /* 0x00000000 */
|
||||
#define IOMUXC_UART4_UART_RTS_B_SELECT_INPUT 0x0934 /* 0x00000000 */
|
||||
#define IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT 0x0938 /* 0x00000000 */
|
||||
#define IOMUXC_UART5_UART_RTS_B_SELECT_INPUT 0x093c /* 0x00000000 */
|
||||
#define IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT 0x0940 /* 0x00000000 */
|
||||
#define IOMUXC_USB_OTG_OC_SELECT_INPUT 0x0944 /* 0x00000000 */
|
||||
#define IOMUXC_USB_H1_OC_SELECT_INPUT 0x0948 /* 0x00000000 */
|
||||
#define IOMUXC_USDHC1_WP_ON_SELECT_INPUT 0x094c /* 0x00000000 */
|
||||
|
||||
#endif /* IMX6_IOMUXREG_H */
|
||||
@ -29,6 +29,13 @@
|
||||
#ifndef IMX_IOMUXVAR_H
|
||||
#define IMX_IOMUXVAR_H
|
||||
|
||||
/*
|
||||
* IOMUX interface functions
|
||||
*/
|
||||
void iomux_set_function(u_int pin, u_int fn);
|
||||
void iomux_set_pad(u_int pin, u_int cfg);
|
||||
u_int iomux_get_pad_config(u_int pin);
|
||||
|
||||
/*
|
||||
* The IOMUX Controller device has a small set of "general purpose registers"
|
||||
* which control various aspects of SoC operation that really have nothing to do
|
||||
|
||||
Loading…
Reference in New Issue
Block a user