- Add support for MCI1 revision 2xx controllers and a work-around for their
"Data Write Operation and number of bytes" erratum. - Use DEVMETHOD_END. - Use NULL instead of 0 for pointers.
This commit is contained in:
Marius Strobl
parent
1472f4f4b9
commit
f7f6865e6d
@ -113,6 +113,7 @@ static void at91_mci_intr(void *);
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/* helper routines */
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static int at91_mci_activate(device_t dev);
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static void at91_mci_deactivate(device_t dev);
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static int at91_mci_is_mci1rev2xx(void);
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#define AT91_MCI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define AT91_MCI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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@ -141,11 +142,16 @@ static void
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at91_mci_init(device_t dev)
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{
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struct at91_mci_softc *sc = device_get_softc(dev);
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uint32_t val;
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WR4(sc, MCI_CR, MCI_CR_MCIEN); /* Enable controller */
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WR4(sc, MCI_IDR, 0xffffffff); /* Turn off interrupts */
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WR4(sc, MCI_DTOR, MCI_DTOR_DTOMUL_1M | 1);
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WR4(sc, MCI_MR, 0x834a); // XXX GROSS HACK FROM LINUX
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val = MCI_MR_PDCMODE;
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val |= 0x34a; /* PWSDIV = 3; CLKDIV = 74 */
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if (at91_mci_is_mci1rev2xx())
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val |= MCI_MR_RDPROOF | MCI_MR_WRPROOF;
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WR4(sc, MCI_MR, val);
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#ifndef AT91_MCI_SLOT_B
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WR4(sc, MCI_SDCR, 0); /* SLOT A, 1 bit bus */
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#else
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@ -303,6 +309,29 @@ at91_mci_deactivate(device_t dev)
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return;
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}
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static int
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at91_mci_is_mci1rev2xx(void)
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{
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switch (AT91_CPU(at91_chip_id)) {
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case AT91_CPU_SAM9260:
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case AT91_CPU_SAM9263:
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#ifdef notyet
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case AT91_CPU_CAP9:
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#endif
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case AT91_CPU_SAM9G10:
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case AT91_CPU_SAM9G20:
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#ifdef notyet
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case AT91_CPU_SAM9RL:
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#endif
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case AT91_CPU_SAM9XE128:
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case AT91_CPU_SAM9XE256:
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case AT91_CPU_SAM9XE512:
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return(1);
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}
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return (0);
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}
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static void
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at91_mci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
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{
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@ -346,6 +375,7 @@ at91_mci_update_ios(device_t brdev, device_t reqdev)
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static void
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at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
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{
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size_t len;
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uint32_t cmdr, ier = 0, mr;
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uint32_t *src, *dst;
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int i;
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@ -397,6 +427,7 @@ at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
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WR4(sc, MCI_MR, mr | (data->len << 16) | MCI_MR_PDCMODE);
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WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
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if (cmdr & MCI_CMDR_TRCMD_START) {
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len = data->len;
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if (cmdr & MCI_CMDR_TRDIR)
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vaddr = cmd->data->data;
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else {
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@ -411,6 +442,15 @@ at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
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vaddr = sc->bounce_buffer;
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src = (uint32_t *)cmd->data->data;
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dst = (uint32_t *)vaddr;
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/*
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* If this is MCI1 revision 2xx controller, apply
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* a work-around for the "Data Write Operation and
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* number of bytes" erratum.
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*/
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if (at91_mci_is_mci1rev2xx() && data->len < 12) {
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len = 12;
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memset(dst, 0, 12);
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}
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if (sc->sc_cap & CAP_NEEDS_BYTESWAP) {
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for (i = 0; i < data->len / 4; i++)
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dst[i] = bswap32(src[i]);
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@ -418,7 +458,7 @@ at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
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memcpy(dst, src, data->len);
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}
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data->xfer_len = 0;
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if (bus_dmamap_load(sc->dmatag, sc->map, vaddr, data->len,
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if (bus_dmamap_load(sc->dmatag, sc->map, vaddr, len,
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at91_mci_getaddr, &paddr, 0) != 0) {
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cmd->error = MMC_ERR_NO_MEMORY;
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sc->req = NULL;
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@ -430,12 +470,12 @@ at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
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if (cmdr & MCI_CMDR_TRDIR) {
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bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_PREREAD);
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WR4(sc, PDC_RPR, paddr);
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WR4(sc, PDC_RCR, data->len / 4);
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WR4(sc, PDC_RCR, len / 4);
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ier = MCI_SR_ENDRX;
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} else {
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bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_PREWRITE);
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WR4(sc, PDC_TPR, paddr);
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WR4(sc, PDC_TCR, data->len / 4);
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WR4(sc, PDC_TCR, len / 4);
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ier = MCI_SR_TXBUFE;
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}
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}
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@ -769,7 +809,7 @@ static device_method_t at91_mci_methods[] = {
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DEVMETHOD(mmcbr_acquire_host, at91_mci_acquire_host),
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DEVMETHOD(mmcbr_release_host, at91_mci_release_host),
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{0, 0},
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DEVMETHOD_END
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};
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static driver_t at91_mci_driver = {
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@ -777,7 +817,8 @@ static driver_t at91_mci_driver = {
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at91_mci_methods,
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sizeof(struct at91_mci_softc),
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};
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static devclass_t at91_mci_devclass;
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DRIVER_MODULE(at91_mci, atmelarm, at91_mci_driver, at91_mci_devclass, 0, 0);
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DRIVER_MODULE(at91_mci, atmelarm, at91_mci_driver, at91_mci_devclass, NULL,
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NULL);
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@ -54,6 +54,9 @@
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/* -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- */
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#define MCI_MR_CLKDIV (0xffu << 0) /* (MCI) Clock Divider */
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#define MCI_MR_PWSDIV (0x3fu << 8) /* (MCI) Power Saving Divider */
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#define MCI_MR_RDPROOF (0x1u << 11) /* (MCI) Read Proof Enable */
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#define MCI_MR_WRPROOF (0x1u << 12) /* (MCI) Write Proof Enable */
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#define MCI_MR_PDCFBYTE (0x1u << 13) /* (MCI) PDC Force Byte Transfer */
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#define MCI_MR_PDCPADV (0x1u << 14) /* (MCI) PDC Padding Value */
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#define MCI_MR_PDCMODE (0x1u << 15) /* (MCI) PDC Oriented Mode */
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#define MCI_MR_BLKLEN 0x3fff0000ul /* (MCI) Data Block Length */
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