o Add support for memory above 256MB on the octeon.
o Force the ebase to be 0x80000000 (the base that we're booted with may need to be respected in the future). o Initialize the clock early so we can initialize the console early o use panic where we can now use it. o Tag some code for parsing the boot records as belonging in the cavium sdk. o remove support for booting on ancient boards... # we make it further in bootstrapping now: interrupts being enabled in the # uarts are now taking us out, it seems, for reasons unknown.
This commit is contained in:
Warner Losh
parent
ff9ab61a59
commit
f92a1e9b89
@ -77,6 +77,7 @@ __FBSDID("$FreeBSD$");
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#define MAX_APP_DESC_ADDR 0xafffffff
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#endif
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static struct pcpu pcpu0;
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extern int *edata;
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extern int *end;
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@ -87,6 +88,16 @@ static void octeon_boot_params_init(register_t ptr);
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static uint64_t ciu_get_intr_sum_reg_addr(int core_num, int intx, int enx);
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static uint64_t ciu_get_intr_en_reg_addr(int core_num, int intx, int enx);
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static __inline void
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mips_wr_ebase(u_int32_t a0)
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{
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__asm __volatile("mtc0 %[a0], $15, 1 ;"
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:
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: [a0] "r"(a0));
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mips_barrier();
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}
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void
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platform_cpu_init()
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{
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@ -638,52 +649,122 @@ void ciu_enable_interrupts(int core_num, int intx, int enx,
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octeon_set_interrupts(cpu_status_bits);
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}
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unsigned long
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octeon_get_clock_rate(void)
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{
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return octeon_cpu_clock;
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}
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static void
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octeon_memory_init(void)
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{
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uint32_t realmem_bytes;
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if (octeon_board_real()) {
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printf("octeon_dram == %llx\n", octeon_dram);
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printf("reduced to ram: %u MB", (uint32_t) octeon_dram >> 20);
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realmem_bytes = (octeon_dram - PAGE_SIZE);
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realmem_bytes &= ~(PAGE_SIZE - 1);
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printf("Real memory bytes is %x\n", realmem_bytes);
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} else {
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/* Simulator we limit to 96 meg */
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realmem_bytes = (96 << 20);
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}
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/* phys_avail regions are in bytes */
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phys_avail[0] = (MIPS_KSEG0_TO_PHYS((vm_offset_t)&end) + PAGE_SIZE) & ~(PAGE_SIZE - 1);
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if (octeon_board_real()) {
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if (realmem_bytes > OCTEON_DRAM_FIRST_256_END)
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phys_avail[1] = OCTEON_DRAM_FIRST_256_END;
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else
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phys_avail[1] = realmem_bytes;
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realmem_bytes -= OCTEON_DRAM_FIRST_256_END;
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realmem_bytes &= ~(PAGE_SIZE - 1);
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printf("phys_avail[0] = %x phys_avail[1] = %x\n",
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phys_avail[0], phys_avail[1]);
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} else {
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/* Simulator gets 96Meg period. */
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phys_avail[1] = (96 << 20);
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}
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/*-
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* Octeon Memory looks as follows:
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* PA
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* 0000 0000 to 0x0 0000 0000 0000
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* 0FFF FFFF First 256 MB memory Maps to 0x0 0000 0FFF FFFF
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*
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* 1000 0000 to 0x1 0000 1000 0000
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* 1FFF FFFF Uncached Bu I/O space.converted to 0x1 0000 1FFF FFFF
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*
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* 2FFF FFFF to Cached 0x0 0000 2000 0000
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* FFFF FFFF all dram mem above the first 512M 0x3 FFFF FFFF FFFF
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*
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*/
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physmem = btoc(phys_avail[1] - phys_avail[0]);
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if ((octeon_board_real()) &&
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(realmem_bytes > OCTEON_DRAM_FIRST_256_END)) {
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/* take out the upper non-cached 1/2 */
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realmem_bytes -= OCTEON_DRAM_FIRST_256_END;
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realmem_bytes &= ~(PAGE_SIZE - 1);
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/* Now map the rest of the memory */
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phys_avail[2] = 0x20000000;
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printf("realmem_bytes is now at %x\n", realmem_bytes);
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phys_avail[3] = ((uint32_t) 0x20000000 + realmem_bytes);
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printf("Next block of memory goes from %x to %x\n",
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phys_avail[2], phys_avail[3]);
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physmem += btoc(phys_avail[3] - phys_avail[2]);
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} else {
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printf("realmem_bytes is %d\n", realmem_bytes);
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}
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realmem = physmem;
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printf("\nTotal DRAM Size 0x%X", (uint32_t) octeon_dram);
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printf("\nBank 0 = 0x%8X -> 0x%8X", phys_avail[0], phys_avail[1]);
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printf("\nBank 1 = 0x%8X -> 0x%8X\n", phys_avail[2], phys_avail[3]);
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printf("\nphysmem: 0x%lx", physmem);
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Maxmem = physmem;
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}
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void
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platform_start(__register_t a0, __register_t a1, __register_t a2 __unused,
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__register_t a3)
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{
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uint64_t platform_counter_freq;
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int i, mem = 0;
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/* Initialize pcpu stuff */
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mips_pcpu0_init();
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octeon_boot_params_init(a3);
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/* XXX octeon boot decriptor has args in it... */
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octeon_ciu_reset();
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octeon_uart_write_string(0, "Platform Starting\n");
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bootverbose = 1;
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if (mem > 0)
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realmem = btoc(mem << 20);
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else
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realmem = btoc(32 << 20);
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for (i = 0; i < 10; i++)
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phys_avail[i] = 0;
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/* phys_avail regions are in bytes */
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phys_avail[0] = MIPS_KSEG0_TO_PHYS((vm_offset_t)&end);
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phys_avail[1] = ctob(realmem);
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physmem = realmem;
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pmap_bootstrap();
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mips_proc0_init();
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init_param1();
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/* TODO: parse argc,argv */
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platform_counter_freq = 330000000UL; /* XXX: from idt */
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mips_timer_init_params(platform_counter_freq, 1);
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mips_timer_early_init(OCTEON_CLOCK_DEFAULT);
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cninit();
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octeon_ciu_reset();
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octeon_boot_params_init(a3);
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bootverbose = 1;
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cpuid_to_pcpu[0] = &pcpu0;
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/*
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* For some reason on the cn38xx simulator ebase register is set to
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* 0x80001000 at bootup time. Move it back to the default, but
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* when we move to having support for multiple executives, we need
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* to rethink this.
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*/
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mips_wr_ebase(0x80000000);
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octeon_memory_init();
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init_param1();
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init_param2(physmem);
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mips_cpu_init();
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pmap_bootstrap();
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mips_proc0_init();
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mutex_init();
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#ifdef DDB
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kdb_init();
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#endif
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platform_counter_freq = octeon_get_clock_rate();
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mips_timer_init_params(platform_counter_freq, 1);
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}
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/* impSTART: This stuff should move back into the Cavium SDK */
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/*
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****************************************************************************************
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*
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@ -788,7 +869,6 @@ uint8_t octeon_mac_addr[6] = { 0 };
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int octeon_core_mask, octeon_mac_addr_count;
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int octeon_chip_rev_major = 0, octeon_chip_rev_minor = 0, octeon_chip_type = 0;
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extern int32_t app_descriptor_addr;
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static octeon_boot_descriptor_t *app_desc_ptr;
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static cvmx_bootinfo_t *cvmx_desc_ptr;
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@ -821,7 +901,6 @@ octeon_process_app_desc_ver_unknown(void)
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octeon_dram = OCTEON_DRAM_DEFAULT;
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octeon_board_rev_major = octeon_board_rev_minor = octeon_board_type = 0;
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octeon_core_mask = 1;
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octeon_cpu_clock = OCTEON_CLOCK_DEFAULT;
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octeon_chip_type = octeon_chip_rev_major = octeon_chip_rev_minor = 0;
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octeon_mac_addr[0] = 0x00; octeon_mac_addr[1] = 0x0f;
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octeon_mac_addr[2] = 0xb7; octeon_mac_addr[3] = 0x10;
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@ -844,13 +923,10 @@ octeon_process_app_desc_ver_6(void)
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(cvmx_bootinfo_t *) ((intptr_t)cvmx_desc_ptr | MIPS_KSEG0_START);
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octeon_cvmx_bd_ver = (cvmx_desc_ptr->major_version * 100) +
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cvmx_desc_ptr->minor_version;
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/* Too early for panic? */
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if (cvmx_desc_ptr->major_version != 1) {
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printf("Incompatible CVMX descriptor from bootloader: %d.%d %p\n",
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panic("Incompatible CVMX descriptor from bootloader: %d.%d %p\n",
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(int) cvmx_desc_ptr->major_version,
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(int) cvmx_desc_ptr->minor_version, cvmx_desc_ptr);
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while (1); /* Never return */
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return 1; /* Satisfy the compiler */
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}
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octeon_core_mask = cvmx_desc_ptr->core_mask;
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@ -876,53 +952,15 @@ octeon_process_app_desc_ver_6(void)
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return 0;
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}
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static int
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octeon_process_app_desc_ver_3_4_5(void)
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{
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octeon_cvmx_bd_ver = octeon_bd_ver;
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octeon_core_mask = app_desc_ptr->core_mask;
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if (app_desc_ptr->desc_version > 3)
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octeon_cpu_clock = app_desc_ptr->eclock_hz;
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else
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octeon_cpu_clock = OCTEON_CLOCK_DEFAULT;
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if (app_desc_ptr->dram_size > 16*1024*1024)
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octeon_dram = (uint64_t)app_desc_ptr->dram_size;
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else
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octeon_dram = (uint64_t)app_desc_ptr->dram_size << 20;
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if (app_desc_ptr->desc_version > 4) {
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octeon_board_type = app_desc_ptr->board_type;
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octeon_board_rev_major = app_desc_ptr->board_rev_major;
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octeon_board_rev_minor = app_desc_ptr->board_rev_minor;
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octeon_chip_type = app_desc_ptr->chip_type;
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octeon_chip_rev_major = app_desc_ptr->chip_rev_major;
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octeon_chip_rev_minor = app_desc_ptr->chip_rev_minor;
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octeon_mac_addr[0] = app_desc_ptr->mac_addr_base[0];
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octeon_mac_addr[1] = app_desc_ptr->mac_addr_base[1];
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octeon_mac_addr[2] = app_desc_ptr->mac_addr_base[2];
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octeon_mac_addr[3] = app_desc_ptr->mac_addr_base[3];
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octeon_mac_addr[4] = app_desc_ptr->mac_addr_base[4];
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octeon_mac_addr[5] = app_desc_ptr->mac_addr_base[5];
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octeon_mac_addr_count = app_desc_ptr->mac_addr_count;
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}
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return 0;
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}
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static void
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octeon_boot_params_init(register_t ptr)
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{
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int bad_desc = 1;
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if (ptr != 0 && ptr < MAX_APP_DESC_ADDR) {
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app_desc_ptr = (octeon_boot_descriptor_t *)(intptr_t)ptr;
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octeon_bd_ver = app_desc_ptr->desc_version;
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if ((octeon_bd_ver >= 3) && (octeon_bd_ver <= 5))
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bad_desc = octeon_process_app_desc_ver_3_4_5();
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else if (app_desc_ptr->desc_version == 6)
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if (app_desc_ptr->desc_version == 6)
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bad_desc = octeon_process_app_desc_ver_6();
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}
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if (bad_desc)
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@ -937,7 +975,9 @@ octeon_boot_params_init(register_t ptr)
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printf(" Octeon Chip: %u Rev %u/%u",
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octeon_chip_type, octeon_chip_rev_major, octeon_chip_rev_minor);
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printf(" Mac Address %02X.%02X.%02X.%02X.%02X.%02X\n",
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octeon_mac_addr[0], octeon_mac_addr[1], octeon_mac_addr[2],
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octeon_mac_addr[3], octeon_mac_addr[4], octeon_mac_addr[5]);
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printf(" Mac Address %02X.%02X.%02X.%02X.%02X.%02X (%d)\n",
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octeon_mac_addr[0], octeon_mac_addr[1], octeon_mac_addr[2],
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octeon_mac_addr[3], octeon_mac_addr[4], octeon_mac_addr[5],
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octeon_mac_addr_count);
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}
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/* impEND: This stuff should move back into the Cavium SDK */
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