MFKernel: do not use __XSCALE__ to detect if clz/pld/ldrd/strd are

available, use _ARM_ARCH_5/_ARM_ARCH_5E instead.

MFC After:	3 days
This commit is contained in:
Olivier Houchard 2007-10-13 12:06:31 +00:00
parent def35d2ca7
commit fa030de012
3 changed files with 9 additions and 9 deletions

View File

@ -49,7 +49,7 @@ ENTRY(ffs)
/* Standard trick to isolate bottom bit in r0 or 0 if r0 = 0 on entry */ /* Standard trick to isolate bottom bit in r0 or 0 if r0 = 0 on entry */
rsb r1, r0, #0 rsb r1, r0, #0
ands r0, r0, r1 ands r0, r0, r1
#ifndef __XSCALE__ #ifndef _ARM_ARCH_5
/* /*
* now r0 has at most one set bit, call this X * now r0 has at most one set bit, call this X
* if X = 0, all further instructions are skipped * if X = 0, all further instructions are skipped

View File

@ -2,7 +2,7 @@
#include <machine/asm.h> #include <machine/asm.h>
__FBSDID("$FreeBSD$"); __FBSDID("$FreeBSD$");
#if !defined(__XSCALE__) || defined(_STANDALONE) #if !defined(_ARM_ARCH_5E) || defined(_STANDALONE)
#include "memcpy_arm.S" #include "memcpy_arm.S"
#else #else
#include "memcpy_xscale.S" #include "memcpy_xscale.S"

View File

@ -103,15 +103,15 @@ ENTRY(memset)
#ifndef _BZERO #ifndef _BZERO
orr r3, r3, r3, lsl #8 /* Extend value to 16-bits */ orr r3, r3, r3, lsl #8 /* Extend value to 16-bits */
#endif #endif
#ifdef __XSCALE__ #ifdef _ARM_ARCH_5E
tst ip, #0x04 /* Quad-align for Xscale */ tst ip, #0x04 /* Quad-align for armv5e */
#else #else
cmp r1, #0x10 cmp r1, #0x10
#endif #endif
#ifndef _BZERO #ifndef _BZERO
orr r3, r3, r3, lsl #16 /* Extend value to 32-bits */ orr r3, r3, r3, lsl #16 /* Extend value to 32-bits */
#endif #endif
#ifdef __XSCALE__ #ifdef _ARM_ARCH_5E
subne r1, r1, #0x04 /* Quad-align if necessary */ subne r1, r1, #0x04 /* Quad-align if necessary */
strne r3, [ip], #0x04 strne r3, [ip], #0x04
cmp r1, #0x10 cmp r1, #0x10
@ -124,7 +124,7 @@ ENTRY(memset)
/* Do 128 bytes at a time */ /* Do 128 bytes at a time */
.Lmemset_loop128: .Lmemset_loop128:
subs r1, r1, #0x80 subs r1, r1, #0x80
#ifdef __XSCALE__ #ifdef _ARM_ARCH_5E
strged r2, [ip], #0x08 strged r2, [ip], #0x08
strged r2, [ip], #0x08 strged r2, [ip], #0x08
strged r2, [ip], #0x08 strged r2, [ip], #0x08
@ -167,7 +167,7 @@ ENTRY(memset)
/* Do 32 bytes at a time */ /* Do 32 bytes at a time */
.Lmemset_loop32: .Lmemset_loop32:
subs r1, r1, #0x20 subs r1, r1, #0x20
#ifdef __XSCALE__ #ifdef _ARM_ARCH_5E
strged r2, [ip], #0x08 strged r2, [ip], #0x08
strged r2, [ip], #0x08 strged r2, [ip], #0x08
strged r2, [ip], #0x08 strged r2, [ip], #0x08
@ -184,7 +184,7 @@ ENTRY(memset)
adds r1, r1, #0x10 /* Partially adjust for extra sub */ adds r1, r1, #0x10 /* Partially adjust for extra sub */
/* Deal with 16 bytes or more */ /* Deal with 16 bytes or more */
#ifdef __XSCALE__ #ifdef _ARM_ARCH_5E
strged r2, [ip], #0x08 strged r2, [ip], #0x08
strged r2, [ip], #0x08 strged r2, [ip], #0x08
#else #else
@ -202,7 +202,7 @@ ENTRY(memset)
bgt .Lmemset_loop4 bgt .Lmemset_loop4
RETeq /* Zero length so just exit */ RETeq /* Zero length so just exit */
#ifdef __XSCALE__ #ifdef _ARM_ARCH_5E
/* Compensate for 64-bit alignment check */ /* Compensate for 64-bit alignment check */
adds r1, r1, #0x04 adds r1, r1, #0x04
RETeq RETeq