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intpm(4) meet style(9). style(9) meet intpm(4).

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This commit is contained in:
John Baldwin 2006-09-13 18:56:39 +00:00
parent 7d7d9e2242
commit fcf43477b8
2 changed files with 581 additions and 532 deletions
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1004
sys/pci/intpm.c
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File diff suppressed because it is too large Load Diff

109
sys/pci/intpmreg.h
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@ -26,52 +26,63 @@
* $FreeBSD$
*/
/*Register Difinition for Intel Chipset with ACPI Support*/
#define PCI_BASE_ADDR_SMB 0x90 /*Where to MAP IO*/
#define PCI_BASE_ADDR_PM 0x40
#define PCI_HST_CFG_SMB 0xd2 /*Host Configuration*/
#define PCI_INTR_SMB_SMI 0
#define PCI_INTR_SMB_IRQ9 8
#define PCI_INTR_SMB_ENABLE 1
#define PCI_SLV_CMD_SMB 0xd3 /*SLAVE COMMAND*/
#define PCI_SLV_SDW_SMB_1 0xd4 /*SLAVE SHADOW PORT 1*/
#define PCI_SLV_SDW_SMB_2 0xd5 /*SLAVE SHADOW PORT 2*/
#define PCI_REVID_SMB 0xd6
#define LSB 0x1
#define PIIX4_SMBHSTSTS 0x00
#define PIIX4_SMBHSTSTAT_BUSY (1<<0)
#define PIIX4_SMBHSTSTAT_INTR (1<<1)
#define PIIX4_SMBHSTSTAT_ERR (1<<2)
#define PIIX4_SMBHSTSTAT_BUSC (1<<3)
#define PIIX4_SMBHSTSTAT_FAIL (1<<4)
#define PIIX4_SMBSLVSTS 0x01
#define PIIX4_SMBSLVSTS_ALART (1<<5)
#define PIIX4_SMBSLVSTS_SDW2 (1<<4)
#define PIIX4_SMBSLVSTS_SDW1 (1<<3)
#define PIIX4_SMBSLVSTS_SLV (1<<2)
#define PIIX4_SMBSLVSTS_BUSY (1<<0)
#define PIIX4_SMBHSTCNT 0x02
#define PIIX4_SMBHSTCNT_START (1<<6)
#define PIIX4_SMBHSTCNT_PROT_QUICK 0
#define PIIX4_SMBHSTCNT_PROT_BYTE (1<<2)
#define PIIX4_SMBHSTCNT_PROT_BDATA (2<<2)
#define PIIX4_SMBHSTCNT_PROT_WDATA (3<<2)
#define PIIX4_SMBHSTCNT_PROT_BLOCK (5<<2)
#define SMBBLOCKTRANS_MAX 32
#define PIIX4_SMBHSTCNT_KILL (1<<1)
#define PIIX4_SMBHSTCNT_INTREN (1)
#define PIIX4_SMBHSTCMD 0x03
#define PIIX4_SMBHSTADD 0x04
#define PIIX4_SMBHSTDAT0 0x05
#define PIIX4_SMBHSTDAT1 0x06
#define PIIX4_SMBBLKDAT 0x07
#define PIIX4_SMBSLVCNT 0x08
#define PIIX4_SMBSLVCNT_ALTEN (1<<3)
#define PIIX4_SMBSLVCNT_SD2EN (1<<2)
#define PIIX4_SMBSLVCNT_SD1EN (1<<1)
#define PIIX4_SMBSLVCNT_SLVEN (1)
#define PIIX4_SMBSLVCMD 0x09
#define PIIX4_SMBSLVEVT 0x0a
#define PIIX4_SMBSLVDAT 0x0c
/*This is SMBus alart response address*/
#define SMBALTRESP 0x18
#ifndef __INTPMREG_H__
#define __INTPMREG_H__
/* Register definitions for non-ICH Intel Chipset SMBUS controllers. */
/* PCI Config Registers. */
#define PCI_BASE_ADDR_SMB 0x90 /* IO BAR. */
#define PCI_BASE_ADDR_PM 0x40
#define PCI_HST_CFG_SMB 0xd2 /*Host Configuration*/
#define PCI_INTR_SMB_SMI 0
#define PCI_INTR_SMB_IRQ9 8
#define PCI_INTR_SMB_ENABLE 1
#define PCI_SLV_CMD_SMB 0xd3 /*SLAVE COMMAND*/
#define PCI_SLV_SDW_SMB_1 0xd4 /*SLAVE SHADOW PORT 1*/
#define PCI_SLV_SDW_SMB_2 0xd5 /*SLAVE SHADOW PORT 2*/
#define PCI_REVID_SMB 0xd6
/* PIXX4 SMBus Registers in the SMB BAR. */
#define PIIX4_SMBHSTSTS 0x00
#define PIIX4_SMBHSTSTAT_BUSY (1<<0)
#define PIIX4_SMBHSTSTAT_INTR (1<<1)
#define PIIX4_SMBHSTSTAT_ERR (1<<2)
#define PIIX4_SMBHSTSTAT_BUSC (1<<3)
#define PIIX4_SMBHSTSTAT_FAIL (1<<4)
#define PIIX4_SMBSLVSTS 0x01
#define PIIX4_SMBSLVSTS_ALART (1<<5)
#define PIIX4_SMBSLVSTS_SDW2 (1<<4)
#define PIIX4_SMBSLVSTS_SDW1 (1<<3)
#define PIIX4_SMBSLVSTS_SLV (1<<2)
#define PIIX4_SMBSLVSTS_BUSY (1<<0)
#define PIIX4_SMBHSTCNT 0x02
#define PIIX4_SMBHSTCNT_START (1<<6)
#define PIIX4_SMBHSTCNT_PROT_QUICK 0
#define PIIX4_SMBHSTCNT_PROT_BYTE (1<<2)
#define PIIX4_SMBHSTCNT_PROT_BDATA (2<<2)
#define PIIX4_SMBHSTCNT_PROT_WDATA (3<<2)
#define PIIX4_SMBHSTCNT_PROT_BLOCK (5<<2)
#define PIIX4_SMBHSTCNT_KILL (1<<1)
#define PIIX4_SMBHSTCNT_INTREN (1)
#define PIIX4_SMBHSTCMD 0x03
#define PIIX4_SMBHSTADD 0x04
#define LSB 0x1
#define PIIX4_SMBHSTDAT0 0x05
#define PIIX4_SMBHSTDAT1 0x06
#define PIIX4_SMBBLKDAT 0x07
#define PIIX4_SMBSLVCNT 0x08
#define PIIX4_SMBSLVCNT_ALTEN (1<<3)
#define PIIX4_SMBSLVCNT_SD2EN (1<<2)
#define PIIX4_SMBSLVCNT_SD1EN (1<<1)
#define PIIX4_SMBSLVCNT_SLVEN (1)
#define PIIX4_SMBSLVCMD 0x09
#define PIIX4_SMBSLVEVT 0x0a
#define PIIX4_SMBSLVDAT 0x0c
/* SMBus alert response address. */
#define SMBALTRESP 0x18
#define SMBBLOCKTRANS_MAX 32
#endif /* !__INTPMREG_H__ */