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Add some debugging and comments about what's going on when reinitialising

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the FIFO.

I still see some corner cases where no RX occurs when it should be
occuring.  It's quite possible that there's a subtle race condition
somewhere; or maybe I'm not programming the RX queues right.

There's also no locking here yet, so any reset/configuration path
state change (ie, enabling/disabling receive from the ioctl, net80211
taskqueue, etc) could quite possibly confuse things.
This commit is contained in:
Adrian Chadd 2012-07-10 07:45:47 +00:00
parent bcbb08ceb5
commit fda21122d0
1 changed files with 20 additions and 1 deletions
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21
sys/dev/ath/if_ath_rx_edma.c
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@ -190,6 +190,12 @@ ath_edma_reinit_fifo(struct ath_softc *sc, HAL_RX_QUEUE qtype)
i = re->m_fifo_head;
for (j = 0; j < re->m_fifo_depth; j++) {
bf = re->m_fifo[i];
DPRINTF(sc, ATH_DEBUG_EDMA_RX,
"%s: Q%d: pos=%i, addr=0x%x\n",
__func__,
qtype,
i,
bf->bf_daddr);
ath_hal_putrxbuf(sc->sc_ah, bf->bf_daddr, qtype);
INCR(i, re->m_fifolen);
}
@ -221,8 +227,21 @@ ath_edma_startrecv(struct ath_softc *sc)
/*
* Entries should only be written out if the
* FIFO is empty.
*
* XXX This isn't correct. I should be looking
* at the value of AR_RXDP_SIZE (0x0070) to determine
* how many entries are in here.
*
* A warm reset will clear the registers but not the FIFO.
*
* And I believe this is actually the address of the last
* handled buffer rather than the current FIFO pointer.
* So if no frames have been (yet) seen, we'll reinit the
* FIFO.
*
* I'll chase that up at some point.
*/
if (ath_hal_getrxbuf(sc->sc_ah, HAL_RX_QUEUE_HP) == 0){
if (ath_hal_getrxbuf(sc->sc_ah, HAL_RX_QUEUE_HP) == 0) {
DPRINTF(sc, ATH_DEBUG_EDMA_RX,
"%s: Re-initing HP FIFO\n", __func__);
ath_edma_reinit_fifo(sc, HAL_RX_QUEUE_HP);