Rework E500 locore.
- split bootstrap code into more modular routines, which will also be used for the non-booting cores - clean up registers usage - improve comments to better reflect reality - eliminate dead or redundant code - other minor fixes This refactoring is a preliminary step before importing dual-core (MPC8572) support. Obtained from: Freescale, Semihalf
This commit is contained in:
parent
51d059c6de
commit
fdd28cb882
@ -1,4 +1,5 @@
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/*-
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* Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski <raj@semihalf.com>
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* Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
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* All rights reserved.
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*
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@ -10,8 +11,6 @@
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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@ -29,8 +28,8 @@
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#include "assym.s"
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#include <machine/param.h>
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#include <machine/asm.h>
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#include <machine/param.h>
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#include <machine/spr.h>
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#include <machine/psl.h>
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#include <machine/pte.h>
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@ -60,206 +59,139 @@ kernel_text:
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__start:
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/*
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* Assumption on a boot loader:
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* Assumptions on the boot loader:
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* - system memory starts from physical address 0
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* - kernel is loaded at 16MB boundary
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* - it's mapped by a single TBL1 entry
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* - TLB1 mapping is 1:1 pa to va
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* - kernel is loaded at 16MB boundary
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* - all PID registers are set to the same value
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* - CPU is running in AS=0
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*
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* Loader register use:
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* Registers contents provided by the loader(8):
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* r1 : stack pointer
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* r3 : metadata pointer
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*
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* We rearrange the TLB1 layout as follows:
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* - find AS and entry kernel started in
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* - find TLB1 entry we started in
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* - make sure it's protected, ivalidate other entries
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* - create temp entry in the second AS (make sure it's not TLB[15])
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* - create temp entry in the second AS (make sure it's not TLB[1])
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* - switch to temp mapping
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* - map 16MB of RAM in TLB1[15]
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* - map 16MB of RAM in TLB1[1]
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* - use AS=1, set EPN to KERNBASE and RPN to kernel load address
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* - switch to to TLB1[15] mapping
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* - switch to to TLB1[1] mapping
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* - invalidate temp mapping
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*
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* locore register use:
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* locore registers use:
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* r1 : stack pointer
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* r2 : unused
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* r3 : kernel_text
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* r4 : _end
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* r5 : metadata pointer
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* r6-r9 : unused
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* r10 : entry we started in
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* r11 : temp entry
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* r12 : AS we started in
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* r13-r31 : auxiliary registers
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* r2 : trace pointer (AP only, for early diagnostics)
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* r3-r27 : scratch registers
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* r28 : kernload
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* r29 : temp TLB1 entry
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* r30 : initial TLB1 entry we started in
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* r31 : metadata pointer
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*/
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/*
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* Move metadata ptr to r5
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* Keep metadata ptr in r31 for later use.
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*/
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mr %r5, %r3
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mr %r31, %r3
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/*
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* Initial cleanup
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*/
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li %r16, 0x200 /* Keep debug exceptions for CodeWarrior. */
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mtmsr %r16
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li %r3, PSL_DE /* Keep debug exceptions for CodeWarrior. */
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mtmsr %r3
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isync
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#if 0
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mtspr SPR_HID0, %r16
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isync
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msync
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mtspr SPR_HID1, %r16
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isync
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#endif
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/* Issue INV_ALL Invalidate on TLB0 */
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li %r16, 0x04
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tlbivax 0, %r16
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isync
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msync
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/* Invalidate all entries in TLB0 */
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li %r3, 0
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bl tlb_inval_all
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/*
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* Use tblsx to locate the TLB1 entry that maps kernel code
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* Locate the TLB1 entry that maps this code
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*/
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bl 1f /* Current address */
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1: mflr %r15
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/* Find entry that maps current address */
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mfspr %r17, SPR_PID0
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slwi %r17, %r17, MAS6_SPID0_SHIFT
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mtspr SPR_MAS6, %r17
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isync
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tlbsx 0, %r15
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/* Copy entry number to r10 */
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mfspr %r17, SPR_MAS0
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rlwinm %r10, %r17, 16, 28, 31
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/* Invalidate TLB1, skipping our entry. */
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mfspr %r17, SPR_TLB1CFG /* Get number of entries */
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andi. %r17, %r17, TLBCFG_NENTRY_MASK@l
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li %r16, 0 /* Start from Entry 0 */
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2: lis %r15, MAS0_TLBSEL1@h /* Select TLB1 */
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rlwimi %r15, %r16, 16, 12, 15
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mtspr SPR_MAS0, %r15
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isync
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tlbre
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mfspr %r15, SPR_MAS1
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cmpw %r16, %r10
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beq 3f
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/* Clear VALID and IPROT bits for other entries */
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rlwinm %r15, %r15, 0, 2, 31
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mtspr SPR_MAS1, %r15
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isync
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tlbwe
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isync
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msync
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3: addi %r16, %r16, 1
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cmpw %r16, %r17 /* Check if this is the last entry */
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bne 2b
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bl 1f
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1: mflr %r3
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bl tlb1_find_current /* the entry number found is returned in r30 */
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bl tlb1_inval_all_but_current
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/*
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* Create temporary mapping in the other Address Space
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* Create temporary mapping in AS=1 and switch to it
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*/
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lis %r17, MAS0_TLBSEL1@h /* Select TLB1 */
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rlwimi %r17, %r10, 16, 12, 15 /* Select our entry */
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mtspr SPR_MAS0, %r17
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isync
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tlbre /* Read it in */
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bl tlb1_temp_mapping_as1
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/* Prepare and write temp entry */
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lis %r17, MAS0_TLBSEL1@h /* Select TLB1 */
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addi %r11, %r10, 0x1 /* Use next entry. */
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rlwimi %r17, %r11, 16, 12, 15 /* Select temp entry */
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mtspr SPR_MAS0, %r17
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isync
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mfspr %r16, SPR_MAS1
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li %r15, 1 /* AS 1 */
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rlwimi %r16, %r15, 12, 19, 19
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mtspr SPR_MAS1, %r16
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li %r17, 0
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rlwimi %r16, %r17, 0, 8, 15 /* Global mapping, TID=0 */
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isync
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tlbwe
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isync
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msync
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mfmsr %r16
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ori %r16, %r16, 0x30 /* Switch to AS 1. */
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bl 4f /* Find current execution address */
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4: mflr %r15
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addi %r15, %r15, 20 /* Increment to instruction after rfi */
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mtspr SPR_SRR0, %r15
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mtspr SPR_SRR1, %r16
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mfmsr %r3
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ori %r3, %r3, (PSL_IS | PSL_DS)
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bl 2f
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2: mflr %r4
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addi %r4, %r4, 20
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mtspr SPR_SRR0, %r4
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mtspr SPR_SRR1, %r3
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rfi /* Switch context */
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/*
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* Invalidate initial entry
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*/
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mr %r22, %r10
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mr %r3, %r30
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bl tlb1_inval_entry
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/*
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* Setup final mapping in TLB1[1] and switch to it
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*/
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/* Final kernel mapping, map in 16 MB of RAM */
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lis %r16, MAS0_TLBSEL1@h /* Select TLB1 */
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li %r17, 1 /* Entry 1 */
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rlwimi %r16, %r17, 16, 12, 15
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mtspr SPR_MAS0, %r16
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lis %r3, MAS0_TLBSEL1@h /* Select TLB1 */
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li %r4, 1 /* Entry 1 */
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rlwimi %r3, %r4, 16, 12, 15
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mtspr SPR_MAS0, %r3
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isync
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li %r16, (TLB_SIZE_16M << MAS1_TSIZE_SHIFT)@l
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oris %r16, %r16, (MAS1_VALID | MAS1_IPROT)@h
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mtspr SPR_MAS1, %r16
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li %r3, (TLB_SIZE_16M << MAS1_TSIZE_SHIFT)@l
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oris %r3, %r3, (MAS1_VALID | MAS1_IPROT)@h
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mtspr SPR_MAS1, %r3 /* note TS was not filled, so it's TS=0 */
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isync
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lis %r19, KERNBASE@h
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ori %r19, %r19, KERNBASE@l
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mtspr SPR_MAS2, %r19 /* Set final EPN, clear WIMG */
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lis %r3, KERNBASE@h
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ori %r3, %r3, KERNBASE@l /* EPN = KERNBASE */
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mtspr SPR_MAS2, %r3
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isync
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bl 5f
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5: mflr %r16 /* Use current address */
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lis %r18, 0xff00 /* 16MB alignment mask */
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and %r16, %r16, %r18
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mr %r25, %r16 /* Copy kernel load address */
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ori %r16, %r16, (MAS3_SX | MAS3_SW | MAS3_SR)@l
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mtspr SPR_MAS3, %r16 /* Set RPN and protection */
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/* Discover phys load address */
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bl 3f
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3: mflr %r4 /* Use current address */
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rlwinm %r4, %r4, 0, 0, 7 /* 16MB alignment mask */
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mr %r28, %r4 /* Keep kernel load address */
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ori %r4, %r4, (MAS3_SX | MAS3_SW | MAS3_SR)@l
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mtspr SPR_MAS3, %r4 /* Set RPN and protection */
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isync
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tlbwe
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isync
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msync
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/* Switch to the above TLB1[1] mapping */
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lis %r18, 0x00ff /* 16MB offset mask */
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ori %r18, %r18, 0xffff
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bl 6f
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6: mflr %r20 /* Use current address */
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and %r20, %r20, %r18 /* Offset from kernel load address */
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add %r20, %r20, %r19 /* Move to kernel virtual address */
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addi %r20, %r20, 32 /* Increment to instr. after rfi */
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li %r21, 0x200
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mtspr SPR_SRR0, %r20
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mtspr SPR_SRR1, %r21
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bl 4f
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4: mflr %r4
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rlwinm %r4, %r4, 0, 8, 31 /* Current offset from kernel load address */
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rlwinm %r3, %r3, 0, 0, 19
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add %r4, %r4, %r3 /* Convert to kernel virtual address */
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addi %r4, %r4, 36
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li %r3, PSL_DE /* Note AS=0 */
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mtspr SPR_SRR0, %r4
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mtspr SPR_SRR1, %r3
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rfi
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/* Save kernel load address for later use */
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lis %r24, kernload@ha
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addi %r24, %r24, kernload@l
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stw %r25, 0(%r24)
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/*
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* Invalidate temp mapping
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*/
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mr %r22, %r11
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mr %r3, %r29
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bl tlb1_inval_entry
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/*
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* Save kernel load address for later use.
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*/
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lis %r3, kernload@ha
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addi %r3, %r3, kernload@l
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stw %r28, 0(%r3)
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/*
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* Setup a temporary stack
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*/
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@ -273,114 +205,198 @@ __start:
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bl ivor_setup
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/*
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* Jump to system initialization code
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*
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* Setup first two arguments for e500_init, metadata (r5) is already in place.
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* Set up arguments and jump to system initialization code
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*/
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lis %r3, kernel_text@ha
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addi %r3, %r3, kernel_text@l
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lis %r4, _end@ha
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addi %r4, %r4, _end@l
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mr %r5, %r31 /* metadata ptr */
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/* Prepare e500 core */
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bl e500_init
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/* Switch to thread0.td_kstack */
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/* Switch to thread0.td_kstack now */
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mr %r1, %r3
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li %r3, 0
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stw %r3, 0(%r1)
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bl mi_startup /* Machine independet part, does not return */
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/* Machine independet part, does not return */
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bl mi_startup
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/* NOT REACHED */
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5: b 5b
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/************************************************************************/
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/* locore subroutines */
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/************************************************************************/
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tlb1_inval_entry:
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lis %r17, MAS0_TLBSEL1@h /* Select TLB1 */
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rlwimi %r17, %r22, 16, 12, 15 /* Select our entry */
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mtspr SPR_MAS0, %r17
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/*
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* Invalidate all entries in the given TLB.
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*
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* r3 TLBSEL
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*/
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tlb_inval_all:
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rlwinm %r3, %r3, 3, 0x18 /* TLBSEL */
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ori %r3, %r3, 0x4 /* INVALL */
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tlbivax 0, %r3
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isync
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tlbre /* Read it in */
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msync
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li %r16, 0
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mtspr SPR_MAS1, %r16
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tlbsync
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msync
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blr
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/*
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* expects address to look up in r3, returns entry number in r30
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*
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* FIXME: the hidden assumption is we are now running in AS=0, but we should
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* retrieve actual AS from MSR[IS|DS] and put it in MAS6[SAS]
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*/
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tlb1_find_current:
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mfspr %r17, SPR_PID0
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slwi %r17, %r17, MAS6_SPID0_SHIFT
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mtspr SPR_MAS6, %r17
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isync
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tlbsx 0, %r3
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mfspr %r17, SPR_MAS0
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rlwinm %r30, %r17, 16, 20, 31 /* MAS0[ESEL] -> r30 */
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/* Make sure we have IPROT set on the entry */
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mfspr %r17, SPR_MAS1
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oris %r17, %r17, MAS1_IPROT@h
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mtspr SPR_MAS1, %r17
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isync
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tlbwe
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isync
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msync
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blr
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/*
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* Invalidates a single entry in TLB1.
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*
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* r3 ESEL
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* r4-r5 scratched
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*/
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tlb1_inval_entry:
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lis %r4, MAS0_TLBSEL1@h /* Select TLB1 */
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rlwimi %r4, %r3, 16, 12, 15 /* Select our entry */
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mtspr SPR_MAS0, %r4
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isync
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tlbre
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li %r5, 0 /* MAS1[V] = 0 */
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mtspr SPR_MAS1, %r5
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isync
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tlbwe
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isync
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msync
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blr
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/*
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* r30 current entry number
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* r29 returned temp entry
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* r3-r5 scratched
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*/
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tlb1_temp_mapping_as1:
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/* Read our current translation */
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lis %r3, MAS0_TLBSEL1@h /* Select TLB1 */
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rlwimi %r3, %r30, 16, 12, 15 /* Select our current entry */
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mtspr SPR_MAS0, %r3
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isync
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tlbre
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/*
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* Prepare and write temp entry
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*
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* FIXME this is not robust against overflow i.e. when the current
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* entry is the last in TLB1
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*/
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lis %r3, MAS0_TLBSEL1@h /* Select TLB1 */
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addi %r29, %r30, 1 /* Use next entry. */
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li %r4, 1
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cmpw %r4, %r29
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bne 1f
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addi %r29, %r29, 1
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1: rlwimi %r3, %r29, 16, 12, 15 /* Select temp entry */
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mtspr SPR_MAS0, %r3
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isync
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mfspr %r5, SPR_MAS1
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li %r4, 1 /* AS=1 */
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rlwimi %r5, %r4, 12, 19, 19
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li %r4, 0 /* Global mapping, TID=0 */
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rlwimi %r5, %r4, 16, 8, 15
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oris %r5, %r5, (MAS1_VALID | MAS1_IPROT)@h
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mtspr SPR_MAS1, %r5
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isync
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tlbwe
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isync
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msync
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blr
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/*
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* Loops over TLB1, invalidates all entries skipping the one which currently
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* maps this code.
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*
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* r30 current entry
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* r3-r5 scratched
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*/
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tlb1_inval_all_but_current:
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mr %r6, %r3
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mfspr %r3, SPR_TLB1CFG /* Get number of entries */
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andi. %r3, %r3, TLBCFG_NENTRY_MASK@l
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li %r4, 0 /* Start from Entry 0 */
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1: lis %r5, MAS0_TLBSEL1@h
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rlwimi %r5, %r4, 16, 12, 15
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mtspr SPR_MAS0, %r5
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isync
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tlbre
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mfspr %r5, SPR_MAS1
|
||||
cmpw %r4, %r30 /* our current entry? */
|
||||
beq 2f
|
||||
rlwinm %r5, %r5, 0, 2, 31 /* clear VALID and IPROT bits */
|
||||
mtspr SPR_MAS1, %r5
|
||||
isync
|
||||
tlbwe
|
||||
isync
|
||||
msync
|
||||
2: addi %r4, %r4, 1
|
||||
cmpw %r4, %r3 /* Check if this is the last entry */
|
||||
bne 1b
|
||||
blr
|
||||
|
||||
/************************************************************************/
|
||||
/* locore subroutines */
|
||||
/************************************************************************/
|
||||
|
||||
ivor_setup:
|
||||
/* Set base address of interrupt handler routines */
|
||||
lis %r21, interrupt_vector_base@h
|
||||
mtspr SPR_IVPR, %r21
|
||||
lis %r3, interrupt_vector_base@h
|
||||
mtspr SPR_IVPR, %r3
|
||||
|
||||
/* Assign interrupt handler routines offsets */
|
||||
li %r21, int_critical_input@l
|
||||
mtspr SPR_IVOR0, %r21
|
||||
li %r21, int_machine_check@l
|
||||
mtspr SPR_IVOR1, %r21
|
||||
li %r21, int_data_storage@l
|
||||
mtspr SPR_IVOR2, %r21
|
||||
li %r21, int_instr_storage@l
|
||||
mtspr SPR_IVOR3, %r21
|
||||
li %r21, int_external_input@l
|
||||
mtspr SPR_IVOR4, %r21
|
||||
li %r21, int_alignment@l
|
||||
mtspr SPR_IVOR5, %r21
|
||||
li %r21, int_program@l
|
||||
mtspr SPR_IVOR6, %r21
|
||||
li %r21, int_syscall@l
|
||||
mtspr SPR_IVOR8, %r21
|
||||
li %r21, int_decrementer@l
|
||||
mtspr SPR_IVOR10, %r21
|
||||
li %r21, int_fixed_interval_timer@l
|
||||
mtspr SPR_IVOR11, %r21
|
||||
li %r21, int_watchdog@l
|
||||
mtspr SPR_IVOR12, %r21
|
||||
li %r21, int_data_tlb_error@l
|
||||
mtspr SPR_IVOR13, %r21
|
||||
li %r21, int_inst_tlb_error@l
|
||||
mtspr SPR_IVOR14, %r21
|
||||
li %r21, int_debug@l
|
||||
mtspr SPR_IVOR15, %r21
|
||||
blr
|
||||
|
||||
/*
|
||||
* void tlb1_inval_va(vm_offset_t va)
|
||||
*
|
||||
* r3 - va to invalidate
|
||||
*/
|
||||
ENTRY(tlb1_inval_va)
|
||||
/* EA mask */
|
||||
lis %r6, 0xffff
|
||||
ori %r6, %r6, 0xf000
|
||||
and %r3, %r3, %r6
|
||||
|
||||
/* Select TLB1 */
|
||||
ori %r3, %r3, 0x08
|
||||
|
||||
isync
|
||||
tlbivax 0, %r3
|
||||
isync
|
||||
msync
|
||||
blr
|
||||
|
||||
/*
|
||||
* void tlb0_inval_va(vm_offset_t va)
|
||||
*
|
||||
* r3 - va to invalidate
|
||||
*/
|
||||
ENTRY(tlb0_inval_va)
|
||||
/* EA mask, this also clears TLBSEL, selecting TLB0 */
|
||||
lis %r6, 0xffff
|
||||
ori %r6, %r6, 0xf000
|
||||
and %r3, %r3, %r6
|
||||
|
||||
isync
|
||||
tlbivax 0, %r3
|
||||
isync
|
||||
msync
|
||||
li %r3, int_critical_input@l
|
||||
mtspr SPR_IVOR0, %r3
|
||||
li %r3, int_machine_check@l
|
||||
mtspr SPR_IVOR1, %r3
|
||||
li %r3, int_data_storage@l
|
||||
mtspr SPR_IVOR2, %r3
|
||||
li %r3, int_instr_storage@l
|
||||
mtspr SPR_IVOR3, %r3
|
||||
li %r3, int_external_input@l
|
||||
mtspr SPR_IVOR4, %r3
|
||||
li %r3, int_alignment@l
|
||||
mtspr SPR_IVOR5, %r3
|
||||
li %r3, int_program@l
|
||||
mtspr SPR_IVOR6, %r3
|
||||
li %r3, int_syscall@l
|
||||
mtspr SPR_IVOR8, %r3
|
||||
li %r3, int_decrementer@l
|
||||
mtspr SPR_IVOR10, %r3
|
||||
li %r3, int_fixed_interval_timer@l
|
||||
mtspr SPR_IVOR11, %r3
|
||||
li %r3, int_watchdog@l
|
||||
mtspr SPR_IVOR12, %r3
|
||||
li %r3, int_data_tlb_error@l
|
||||
mtspr SPR_IVOR13, %r3
|
||||
li %r3, int_inst_tlb_error@l
|
||||
mtspr SPR_IVOR14, %r3
|
||||
li %r3, int_debug@l
|
||||
mtspr SPR_IVOR15, %r3
|
||||
blr
|
||||
|
||||
/*
|
||||
@ -495,7 +511,7 @@ tmpstack:
|
||||
#define INTRCNT_COUNT 256 /* max(HROWPIC_IRQMAX,OPENPIC_IRQMAX) */
|
||||
|
||||
GLOBAL(kernload)
|
||||
.long
|
||||
.long 0
|
||||
GLOBAL(intrnames)
|
||||
.space INTRCNT_COUNT * (MAXCOMLEN + 1) * 2
|
||||
GLOBAL(eintrnames)
|
||||
|
Loading…
Reference in New Issue
Block a user