For OMAP4, the old values for 1MHz gave a bus frequency of about 890KHz.
The new numbers hit 1MHz exactly.
For AM335x the prescaler values are adjusted to give a 24MHz clock for
all 3 standard speeds, as the manual recommends (as near as we can tell,
there are errors and typos apparent in the document). Also, 1MHz speed
is added, and has been tested successfully on a BeagleboneWhite board.
PR: 195009
The current support for controlling i2c bus speed is an inconsistant mess.
There are 4 symbolic speed values defined, UNKNOWN, SLOW, FAST, FASTEST.
It seems to be universally assumed that SLOW means the standard 100KHz
rate from the original spec. Nothing ever calls iicbus_reset() with a
speed of FAST, although some drivers would treat it as the 400KHz standard
speed. Mostly iicbus_reset() is called with the speed set to UNKNOWN or
FASTEST, and there's really no telling what any individual driver will do
with those.
The speed of an i2c bus is limited by the speed of the slowest device on
the bus. This means that generally the bus speed needs to be configured
based on the board/system and the components within it. Historically for
i2c we've configured with device hints. Newer systems use FDT data and it
documents a clock-frequency property for i2c busses. Hobbyists and
developers are likely to want on the fly changes. These changes provide
all 3 methods, but do not require any existing drivers to change to use
the new facilities.
This adds an iicbus method, iicbus_get_frequency(dev, speed) that gets the
frequency for the requested symbolic speed. If the symbolic speed is SLOW
or if there is no speed configured for the bus, the returned value is
100KHz, always. Otherwise, if bus speed is configured by hints, fdt,
tunable, or sysctl, that speed is returned. It also adds a helper
function, iicbus_init_frequency() that any bus driver subclassed from
iicbus can initialize the frequency from some other source of info.
Initial driver implementations are provided for Freescale and TI.
Differential Revision: https://reviews.freebsd.org/D1174
PR: 195009
unit 0.
It seems that this 'simplification' was copied to all GPIO drivers in tree.
This fix a bug where a GPIO controller could fail to attach its children
(gpioc and gpiobus) if another GPIO driver attach first.
For an unkown reason (at moment), sometimes if_cpsw cannot read from PHY
and fails to attach calling cpsw_detach() which end up in a panic.
Fix it by doing the proper check before detach the miibus and also fix the
leak of few variables.
And to actually make it work, ether_ifattach() has to be moved to the end
of cpsw_attach() to avoid a race where calling ether_ifdetach() before
domain_init() (which will only run later on) would make it crash at
INP_INFO_RLOCK() on in_pcbpurgeif0().
Tested on: BBB (am335x)
MFC after: 1 week
to be present. Thsi creates a new per-SoC driver that handles probe and
setting/getting the gpio flags.
Differential Revision: https://reviews.freebsd.org/D943
Reviewed by: loos, rpaulo
MFC after: 1 week
The TI watchdog timer is present on BeagleBone's. Since 2014, U-Boot
has been booting the BeagleBone with the watchdog enabled. We need to
disable it on boot to avoid a spurious reset.
The timer isn't exactly precise, but it will do as a watchdog. This
is also a reflection of the watchdog(9) API.
In the future, we could handle interrupts, but the watchdog(9) API
needs to be a bit smarter before that can happen.
Differential Revision: https://reviews.freebsd.org/D965
Reviewed by: andrew
MFC after: 1 week
Relnotes: yes
few changes to drivers, no kernel config was added. As the SoCs are quite
old and the code is unmaintained start the process of removing support by
deleting the header file and code that depends on it along with the macro
SOC_OMAP3. Other Ti SoCs shouldn't be affected, other than for us to have
less code to maintain.
Differential Revision: https://reviews.freebsd.org/D936
Reviewed by: rpaulo, loos
. interrupt storm detected on "intr70:"; throttling interrupt source;
. Added access serialization on iicbus_transfer(), previously there was
no such protection and a new transfer could easily confuse the
controller;
. Add error checkings (i.e. stop the transfer when a error is detected
and do _not_ overwrite the previous error);
. On command done interrupt do not assume that the transfer was finished
sucessfully as we will receive the command done interrupt even after
errors;
. Simplify the FIFO handling;
. Reset the FIFO between the transfers as the FIFO may contain data from
the last (failed) transfer;
. Fix the iicbus speed for AM335x, which in turn will make better use of
the I2C noise filter (set to one internal clock cycle);
. Move the read and write handler to ithread instead of notifying the
requesting thread with wakeup(9);
. Fix the comments based on OMAP4 TRM.
The above changes allows me to read the EDID from my HDMI monitor on BBB
with gonzo's patches to support TDA19988 (which does 128 bytes reads) and
repeatedly scan the iicbus (with a modified i2c(8)) without lock up the bus.
Phabric: D465
(7-bit device address << 1), always leaving the room for the read/write bit.
This commit convert ti_i2c and revert r259127 on bcm2835_bsc to make them
compatible with 8-bit addresses. Previous to this commit an i2c device
would have different addresses depending on the controller it was attached
to (by example, when compared to any iicbb(4) based i2c controller), which
was a pretty annoying behavior.
Also, update the PMIC i2c address on beaglebone* DTS files to match the new
address scheme.
Now the userland utilities need to do the correct slave address shifting
(but it is going to work with any i2c controller on the system).
Discussed with: ian
MFC after: 2 weeks
The ti_i2c controller only works in the master mode and the i2c address
passed on iicbus_reset() is used to set the controller slave address when
operating as an i2c slave (which isn't currently supported).
When talking to a slave, the slave address is correctly provided to
ti_i2c_tranfer().
through a voltage divisor (R163 and R164 on page 4 of BBB schematic).
Add a note about this on ti_adc(4) man page. The ti_adc(4) man page will
first appear on 10.1-RELEASE.
MFC after: 1 week
Suggested by: Sulev-Madis Silber (ketas)
Manual page reviewed by: brueffer (D127)
and the actual PWM frequency.
Enforce the maximum value for the period sysctl.
The frequency systcl now allows the direct setting of the PWM frequency (it
will try to find the better clkdiv and period for a given frequency, i.e.
the ones that will give the better PWM resolution).
This allows the use lower frequencies on the PWM. Without changing the
clock prescaler the minimum PWM frequency was 1.52kHz.
PWM frequencies checked with an osciloscope.
PWM output tested with some R/C servos at 50Hz.
memory ordering model allows writes to different devices to complete out
of order, leading to a situation where the write that clears an interrupt
source at a device can complete after a write that unmasks and EOIs the
interrupt at the interrupt controller, leading to a spurious re-interrupt.
This adds a generic barrier function specific to the needs of interrupt
controllers, and calls that function from the GIC and TI AINTC controllers.
There may still be other soc-specific controllers that need to make the call.
Reviewed by: cognet, Svatopluk Kraus <onwahe@gmail.com>
MFC after: 3 days
platform code, it is expected these will be merged in the future when the
ARM code is more complete.
Until more boards can be tested only use this with the Raspberry Pi and
rrename the functions on the other SoCs.
Reviewed by: ian@
While it is the recommended initialization procedure, it hangs on the reset
of the second GPIO module on pandaboard.
Removes the module reset for now as more investigation would be needed.
Reported by: jceel
On AM335x each one of the four GPIO banks has two physical interrupt
lines, so we now allocate resources and setup our interrupt handler for
all the (8) available interrupts.
On OMAP3 and OMAP4 there is only one interrupt for each GPIO bank (6
banks, 6 interrupts), but there are two set of registers where the
first one is used to setup the delivery of interrupts to the MPU and
the second set, setup the delivery of interrupts to the DSP.
On AM335x, each set of registers controls each one of the interrupt
lines.
- Remove nonexistent registers for OMAP4 and AM335x, replace their use with
the correct ones for these SoCs.
- Remove stray whitespace.
Based on OMAP3, OMAP4 and AM335x TRMs.
Tested on Beaglebone-black.
- Don't allow high-speed mode on OMAP4 due to hardware erratum.
- Check the proper bit in the status register when waiting for the
controller to come out of reset.
- Add handling for the "non-removable" fdt property by always returning
"card is present" status.
- Add the non-removable property for the MMC card on a Beaglebone Black.
- Add the non-removable property for Pandaboard as a workaround.
For Pandaboard the card detect pin is handled by the twl6030 fpga device
which gets an interrupt on pin change and then has to query the fpga
for the actual status. We don't have code to do that yet.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>
errors.
Reset the GPIO module during the initialization. This is guaranteed to be
the same as a hardware reset. Tested on AM335x (BBB) and checked against
the omap3 and omap4 TRM.
Do a better job freeing resources when there are errors and on
ti_gpio_detach().
description was eaten by the dog (or an editor crash or something).
Add variable-frequency support to the arm mpcore eventtimer driver.
This allows a platform's early init code to tell the mpcore driver that the
clock frequency can vary. That causes the mpcore driver to register an
eventtimer, but not a timecounter. The platform has to provide a time
counter using some other fixed-frequency clock, but can still use the
per-cpu goodness of the mpcore hardware for event timers.
When the platform support code does something to change the frequency of
the CPU clocks (power saving, thermal management) it must tell the mpcore
driver code about it using arm_tmr_change_frequency().
The ADC has a 12bit resolution and its raw output can be read via sysctl(8)
interface.
The driver allows the setup of ADC clock, samples average and open delay
(the number of clock cycles to wait before start the conversion).
The TSC_ADC module is set in the general purpose mode (no touchscreen
support).
Tested on Beaglebone-black.
Written based on AM335x TRM.
Reviewed by: rpaulo
Approved by: adrian (mentor)
Tested by: me, Brian J. McGovern, Sulev-Madis Silber (ketas)
