4 Commits

Author	SHA1	Message	Date
Adrian Chadd	7afd1d0205	The AR71xx has APB interrupts in the MISC registers from 0-7, later ... chips have more. So for now, let's allow more. We should teach the apb code to just reject interrupts that lie outside what the chip can do at runtime.	2014-03-16 08:39:46 +00:00
Oleksandr Tymoshenko	2839b59a94	- Add intr counters for APB interrupts	2009-11-18 22:53:05 +00:00
Oleksandr Tymoshenko	ccf8f87398	- Handle memory requests on apb level, do not pass them up to ... nexus - Unmask IRQ in bus_intr_setup - Do not count timer IRQ (IRQ0) as stray	2009-05-06 02:31:07 +00:00
Oleksandr Tymoshenko	fd7391fc0c	- Revert changes accidentally killed by merge operation	2009-04-14 22:53:22 +00:00