the right register bank for the framebuffer. Disable the assigned-addresses
path on SPARC since it is just a hack for IBM PPC systems and was neither
relevant for nor worked on SPARC anyway.
vm_phys_fictitious_to_vm_page should not be called directly, even when
operating on a range that has been registered using
vm_phys_fictitious_reg_range. PHYS_TO_VM_PAGE should be used instead
because on arches that use VM_PHYSSEG_DENSE the page might come
directly from vm_page_array.
Reported by: nwhitehorn
Tested by: nwhitehorn, David Mackay <davidm.jx8p@gmail.com>
Sponsored by: Citrix Systems R&D
- Replace the global driver lock with a per-instance device lock.
- Use the per-instance device lock instead of Giant for the CAM sim lock.
- Add global locks to protect the adapter list and DPC queues.
- Use wakeup() and mtx_sleep() to wait for certain events like the
controller going idle rather than polling via timeouts passed to
tsleep().
- Use callout(9) instead of timeout(9).
- Mark the interrupt handler MPSAFE.
- Remove compat shims for FreeBSD versions older than 8.0.
Reviewed by: Steve Chang <ychang@highpoint-tech.com>
- Use the existing vbus locks instead of Giant for the CAM sim lock.
- Use callout(9) instead of timeout(9).
- Mark the interrupt handler MPSAFE.
- Don't attempt to pass data in the softc from probe() to attach().
- Remove compat shims for FreeBSD versions older than 8.0.
Reviewed by: Steve Chang <ychang@highpoint-tech.com>
- Use the existing vbus locks instead of Giant for the CAM sim lock.
- Use callout(9) instead of timeout(9).
- Mark the interrupt handler MPSAFE.
- Don't attempt to pass data in the softc from probe() to attach().
- Remove compat shims for FreeBSD versions older than 8.0.
Reviewed by: Steve Chang <ychang@highpoint-tech.com>
- Use callout(9) instead of timeout(9).
- Use the existing hba lock as the CAM sim lock instead of Giant.
- Mark interrupt handler MPSAFE.
- Reorder detach and destroy the hba lock in detach.
Reviewed by: Steve Chang <ychang@highpoint-tech.com>
- Cleanup some register reads and writes to use existing register
access macros.
- Ensure code which only applies to the control endpoint is not run
for other endpoints in the data transfer path.
MFC after: 3 days
handled by creator(4) (Sun Creator 3D, Elite 3D, etc.). This provides
vt(4) consoles on all devices currently supported by syscons on sparc64.
The driver should also be easily adaptable to support newer Sun framebuffers
such as the XVR-500 and higher.
Many thanks to dumbbell@ (Jean-Sebastien Pedron) for testing this remotely
during development.
ethernet class.
Note: This is untested as I do not have a device like this. That is
reflected in the MFC timeout.
PR: 192345
Submitted by: rozhuk.im gmail.com
MFC after: 4 weeks
Also disable a couple of ACPI devices that are not usable under Dom0.
To this end a couple of booleans are added that allow disabling ACPI
specific devices.
Sponsored by: Citrix Systems R&D
Reviewed by: jhb
x86/xen/xen_nexus.c:
- Return BUS_PROBE_SPECIFIC in the Xen Nexus attachement routine to
force the usage of the Xen Nexus.
- Attach the ACPI bus when running as Dom0.
dev/acpica/acpi_cpu.c:
dev/acpica/acpi_hpet.c:
dev/acpica/acpi_timer.c
- Add a variable that gates the addition of the devices.
x86/include/init.h:
- Declare variables that control the attachment of ACPI cpu, hpet and
timer devices.
Minor fixes to make the Xen Dom0 console work. This includes always
returning there's pending input in xencons_has_input, because on Dom0
there's no shared ring and we cannot test the indexes. The second
fix is to use the CONSOLEIO_read hypercall in order to read input
data from the Xen console.
Sponsored by: Citrix Systems R&D
dev/xen/console/xencons_ring.c:
- Always return true in xencons_has_input for Dom0.
- Implement Dom0 console support for xencons_handle_input.
bridges in strange ways, either rendering them unable to detect
insertion and removal events, or possibly unable to read from the
device behind the bridge.
This fixes at least one laptop, a Toshiba Tecra M5 with a Texas
Instruments PCxx12 (d=0x8039 v=0c104c) bridge. The very similar
Tecra M9 has the same bridge, but worked fine without this change.
The bridge chip has no I/O port BAR, and there is nothing in the spec
to suggest I/O decoding should be enabled; however enabling it fixes
the issue. Add an XXX comment to this effect.
Discussed with: jhb, imp
MFC after: 2 weeks
Reorganize struct sge_iq. Make the iq entry size a compile time
constant. While here, eliminate RX_FL_ESIZE and use EQ_ESIZE directly.
MFC after: 2 weeks
In the mmcsd layer use this value to populate disk->d_ident. Also set
disk->d_descr to the full set of card identification info (includes vendor,
model, manufacturing date, etc).
