The advanced stage of computer assisted hardware design and
verification is aptly illustrated by the fact that this is necessary
because only the first ports in a single-chip, dual-port async
PC-Card product lacks this register.
aic79xx.c:
o Remove redundant ahd_update_modes() call.
o Correct panic in diagnostic should state corruption cause
the SCB Id to be invalid during a selection timeout.
o Add workaround for missing BUSFREEREV feature in Rev A silicon.
o Corect formatting nits.
o Use register pretty printing in more places.
o Save and restore our SCB pointer when updating the waiting queue
list for an "expected" LQ-out busfree.
o In ahd_clear_intstat, deal with the missing autoclear in the
CLRLQO* registers.
o BE fixup in a diagnostic printf.
o Make sure that we are in the proper mode before disabling
selections in ahd_update_pending_scbs.
o Add more diagnostics.
o task_attribute_nonpkt_tag -> task_attribute: we don't need a
nonpkt_tag field anymore for allowing all 512 SCBs to be
used in non-packetized connections.
o Negotiate HOLD_MCS to U320 devices.
o Add a few additional mode assertions.
o Restore the chip mode after clearing out the qinfifo so that
code using ahd_abort_scbs sees a consistent mode.
o Simplify the DMA engine shutdown routine prior to performing
a bus reset.
o Perform the sequencer restart after a chip reset prior to
setting up our timer to poll for the reset to be complete.
On some OSes, the timer could actually pre-empt us and order
is important here.
o Have our "reset poller" set the expected mode since there is
no guarantee of what mode will be in force when we are called
from the OS timer.
o Save and restore the SCB pointer in ahd_dump_card_state(). This
routine must not modify card state.
o Ditto for ahd_dump_scbs().
aic79xx.h:
o Add a few more chip bug definitions.
o Align our tag on a 32bit boundary.
aic79xx.reg:
aic79xx.seq:
o Start work on removing workarounds for Rev B.
o Use a special location in scratch from for stroring
our SCBPTR during legacy FIFO allocations. This corrects
problems in mixed packetized/non-packetized configurations
where calling into a FIFO task corrupted our SCBPTR.
o Don't rely on DMA priority to guarantee that all data in
our FIFOs will flush prior to a command completion notification
going out of the command channel. We've never seen this assumption
fail, but better safe than sorry.
o Deal with missing BUSFREEREV feature in H2A.
o Simplify disconnect list code now that the list will always
have only a single entry.
o Implement the AHD_REG_SLOW_SETTLE_BUG workaround.
o Swith to using "REG_ISR" for local mode scratch during
our ISR.
o Add a missing jmp to the data_group_dma_loop after our
data pointers have been re-initialized by the kernel.
o Correct test in the bitbucket code so that we actually
wait for the bitbucket to complete before signaling the
kernel of the overrun condition.
o Reposition pkt_saveptrs to avoid a jmp instruction.
o Update a comment to reflect that the code now waits for
a FIFO to drain prior to issuing a CLRCHN.
aic79xx_inline.h:
o Remove unused untagged queue handling code.
o Don't attempt to htole64 what could be a 32bit value.
aic79xx_pci.c:
o Set additional bug flags for rev A chips.
aac driver dependent on the linux emulation module. This was
especially bad for the release engineers who tried to move the
aac driver from the kernel onto the drivers floppy. The linux
compat bits for this driver are now in their own driver, aac_linux.
It can be loaded as a module or compiled into the kernel. For
the latter case, the AAC_COMPAT_LINUX option is needed, along with
the COMPAT_LINUX option.
I've tested this in every configuration I can think of. This is an
MFC candidate for 4.7.
Idea from: rwatson
MFC after: 3 days
Linux driver defines 0x103[B-E] so add those as well.
Obtained from: Intel Linux e100 driver
MFC: Immediately if re@ allows it, otherwise after 4.7-RELEASE
of 1024- Ultra4 256). Rename 'requests' tag to 'request_pool' for clarity.
Make sure we do correct xpt_freeze_simq/CAM_RELEASE_SIMQ if we run out
of chip resources.
MFC after: 6 days
In mpttimeout, call mpt_intr just on the offchance that we missed
an interrupt. We can check to see whether or not the command that
is timing out got completed.
When we *do* decide to timeout a command, set the command state to
REQ_TIMEOUT and then invoke another timeout (hz/10)- mpttimeout2.
This allows us to catch a couple cases we've seen where the command
we timed out on in fact is ready to be completed by the firmware.
In any case, it's only after mpttimeout2 is called that we actually
take down the private state and free the request itself. CAM has
been notified in mpttimeout anyway. This whole area should be redone,
but that will take 105% of my available game time for this month.
Fix a couple of missing (and not useful, at presnet) CAMLOCK_2_MPTLOCK
and MPTLOCK_2_CAMLOCK locations.
Split mpt_notify into mpt_ctlop, which handles all reply completions
that have 0x800000000 or'd into the ContextID. This function can, in
fact, call mpt_event_notify_reply, which handles the traditional
async event notifications. While we're at it, put in the extremely
important (but currently untested) code that send back an Ack to
an Event Notification (if the Event Notification is marked with
AckRequired). Note that an Ack also generates another ctlop completion,
tra la.
Fix up mpt_done substantially to try and get how we plug into CAM
correctly done. Remove bogus CAM_RELEASE_SIMQ settings.
Do some cleanups in mpt_action that are related to speed negotiation
for Ultra4 cards. This is an area that is still quite fragile and
worrisome as config data being read back often doesn't make sense or
jibe with the documentation.
At any rate, after these changes were done, I was finally able to
get Lars Eggert's dual 320M disk system to stay up under load all
weekend- hopefully we're in good enough for now shape.
MFC after: 1 week
Define the CFG_DAGA_OFF offset as 128 bytes instead of 40- gives us
a more reasonable headroom.
When reading a config page, zero out the entire request area- not just
the length of the request. This is because we cleverly (cheezily) return
configuration data back into the allocated request area, so it's nice
to make sure we start with a clean area to write on.
MFC after: 1 week
Instead, based upon whether ISP_DAC_SUPPORTED is defined, typedef
isp_dma_addr_t appropriately.
If ISP_DAC_SUPPORTRED is defined, the DMA_WD2/DMA_WD3 macros do something
useful, else they define to '0'.
defined, we set the address space limitation to BUS_SPACE_UNRESTRICTED,
otherwise to BUS_SPACE_MAXADDR_32BIT.
If we have a 1240, ULTRA2 or better, or an FC card, the boundary limit
is BUS_SPACE_UNRESTRICTED and segment limit is BUS_SPACE_MAXADDR_32BIT.
The older 1020/1040 cards have boundary and segment limits of
BUS_SPACE_MAXADDR_24BIT.
disabling memory write invalidate unconditionally. It looks like
they've decided that MWI just doesn't work with these devices.
Also, remove now-irrelevant code that set PCI write boundary values
based on the cache line size.
MFC after: 2 weeks
