by rman_get_virtual(9) to access device registers sparc64 currently cares
about.
Ideally ata(4) should just be converted to access these using bus_space(9)
read/write functions instead as there's really no reason to do it the
former way. However, this part of ata-siliconimage.c should go away in
favor of siis(4) sooner or later anyway and I don't have the hardware to
actually test the SX4 bits of ata-promise.c.
Also ideally the other architectures should also properly handle the
BUS_SPACE_MAP_LINEAR flag of bus_space_map(9) so this code wouldn't need
to be #ifdef'ed.
- for the legacy PCI ATA channels move channel number out of the device
description, same as it is for ahci(4), siis(4) and mvs(4);
- add device description for the ISA ATA channels.
option is defined. This sysctl can be queried by feature_present(3).
Query for this feature in /sbin/atacontrol and /usr/sbin/burncd.
If these utilities detect that ATA_CAM is enabled, then these utilities
will error out. These utilities are compatible with the old ATA
driver, but are incomptible with the new ATA_CAM driver. By erroring out,
we give end-users an idea as to what remedies to use, and reduce the need for them
to file PR's. For atacontrol, camcontrol must be used instead,
and for burncd, alternative utilties from the ports collection must be used
such as sysutils/cdrtools.
In future, maybe someone can re-write burncd to work with ATA_CAM,
but at least for now, we give a somewhat useful error message to end users.
PR: 160979
Reviewed by: jh, Arnaud Lacombe <lacombar at gmail dot com>
Reported by: Joe Barbish <fbsd8 at a1poweruser dot com>
MFC after: 3 days
Mac with this chipset does not initialize AHCI mode unless it is started
from EFI loader. However, legacy ATA mode works.
Submitted by: jkim@ (original version)
Approved by: re (kib)
MFC after: 1 week
accessing SATA registers. Unserialized access under heavy load caused
wrong speed reporting and potentially could cause device loss.
- To free memory and other resources (including above), allocated
during chipinit() method call on attach, add new chipdeinit() method,
called during driver detach.
Submitted by: Andrew Boyer <aboyer@averesystems.com> (initial version)
Approved by: re (kib)
MFC after: 1 week
but has only 2 SATA ports instead of 4. The worst part is that SStatus and
SError registers for missing ports are not implemented and return wrong
values (0xffffffff), that caused infinite reset loop.
Just ignore that SError value while I found no better way to identify them.
should respond with all zeroes to any access to slave registers. Test with
PATA devices confirmed such behavior. Unluckily, Intel SATA controllers in
legacy emulation mode behave differently, not making any difference between
ATA and ATAPI devices. It causes false positive slave device detection and,
as result, command timeouts.
To workaround this problem, mask result of legacy-emulated soft-reset with
the device presence information received from the SATA-specific registers.
This improves hard-reset and hot-plug on these ports.
- Device with ID 0x29218086 is a 2-port variant of ICH9 in legacy mode.
Skip probing for nonexistent slave devices there.
It allows to avoid false positive device detection under Xen, that caused
long probe delays due to subsequent IDENTIFY command timeouts.
MFC after: 1 month
the ataahci(4) and atamarvell(4) drivers share it between the host and
the controller.
- Spell some zeros as BUS_DMA_WAITOK when used as bus_dmamem_alloc() flags.
MFC after: 2 weeks
- SMBus Controller
- SATA Controller
- HD Audio Controller
- Watchdog Controller
Thanks to Seth Heasley (seth.heasley@intel.com) for providing us code.
MFC after 3 days
via AHCI-like memory resource at BAR(5). Use it if BIOS was so kind to
allocate memory for that BAR. This allows hot-plug support and connection
speed reporting.
MFC after: 2 weeks
i.e. alignment, max_address, max_iosize and segsize (only max_address is
thought to have an negative impact regarding this issue though), after
calling ata_dmainit() either directly or indirectly so these values have
no effect or at least no effect on the DMA tags and the defaults are used
for the latter instead. So change the drivers to set these parameters
up-front and ata_dmainit() to honor them.
Reviewd by: mav
MFC after: 1 month
- Implement proper combined mode decoding for Intel controllers to properly
identify SATA and PATA channels and associate ATA channels with SATA ports.
This fixes wrong reporting and in some cases hard resets to wrong SATA ports.
- Improve SATA registers support to handle hot-plug events and potentially
interface errors. For ICH5/6300ESB chipsets these registers accessible via
PCI config space. For later ones they may be accessible via PCI BAR(5).
- For controllers not generating interrupts on hot-plug events, implement
periodic status polling. Use it to detect hot-plug on Intel and VIA
controllers. Same probably could also be used for Serverworks and SIS.
K2 SATA controllers. The chip's status register must be read first, and
as a long, for other registers to be correctly updated after a command, and
this includes the command sequence in device detection as well as the
previously handled case after interrupts. While here, clean up some
previous hacks related to this controller.
Reported by: many
Reviewed by: mav
MFC after: 3 weeks
response to DMA activate FIS under certain circumstances. This is
recommended fix from chip datasheet. If triggered, this bug most likely
cause write command timeout.
MFC after: 2 weeks
value 0xff. On hot-plug this value confuses ata_generic_reset() device
presence detection logic. As soon as we already know drive presence from
SATA hard reset, hint ata_generic_reset() to wait for device signature
until success or full timeout.
Do not grab lock while setting up interrupt, as it causes LOR with
allocation code. Instead make interrupt handler check that CAM bus
initialization completed before touching it.
While there, slightly improve attach errors handling.
Reported by: kib
