Commit Graph

2505 Commits

Author SHA1 Message Date
Warner Losh
32d5c97723 Remove NetBSD implementation details not relevant to FreeBSD. 2014-05-23 00:21:02 +00:00
Ian Lepore
97bbab9993 Map device memory using PTE_DEVICE attributes, and also ensure that the
shared flag is set on normal-memory mappings made via pmap_kenter() for SMP.

The "shared flag" part of this change isn't obvious from the diff, here's
the deal... by using the array of preformatted page table entry templates
instead of constructing the PTE from scratch, we automatically get the
right attribute bits set for both caching and shared.

MFC after:	1 week
2014-05-22 23:38:17 +00:00
Hans Petter Selasky
5c657683bb Optimise reading of pending interrupt registers. If there are no
pending interrupt bits, skip the bit iteration loop.

Reviewed by:	ian @
2014-05-20 15:03:23 +00:00
Andrew Turner
101355bc67 Allow us to compile the Ti iic driver for both OMAP4 and AM335x.
MFC after:	1 week
2014-05-17 18:52:20 +00:00
Andrew Turner
f37128c048 Move the Ti SoCs to use the ARM platform. This should help allowing a
single kernel to work on both PandaBoard and BeagleBone.
2014-05-17 18:35:22 +00:00
Andrew Turner
87ff982083 Add FDT_PLATFORM_DEF2 for when there are multiple platforms needing to use
the same platform methods.
2014-05-17 18:02:46 +00:00
Andrew Turner
92e7f50a4e Fix a comment s/initarm_/platform_/ 2014-05-17 11:29:44 +00:00
Andrew Turner
27521ff8e4 Add the start of the ARM platform code. This is based on the PowerPC
platform code, it is expected these will be merged in the future when the
ARM code is more complete.

Until more boards can be tested only use this with the Raspberry Pi and
rrename the functions on the other SoCs.

Reviewed by:	ian@
2014-05-17 11:27:36 +00:00
Gavin Atkinson
015280f64c Fix spelling mistake in comment.
Spotted during:	http://www.bsdcan.org/2014/schedule/events/484.en.html
2014-05-16 21:20:13 +00:00
Ruslan Bukin
3d0bf6b1d0 Fix return value. Should be logic one or zero. 2014-05-15 10:06:59 +00:00
Mark Murray
7ff2eaaad3 Give suitably-endowed ARMs a register similar to the x86 TSC register.
Here, "suitably endowed" means that the System Control Coprocessor
(#15) has Performance Monitoring Registers, including a CCNT (Cycle
Count) register.

The CCNT register is used in a way similar to the TSC register in
x86 processors by the get_cyclecount(9) function. The entropy-harvesting
thread is a heavy user of this function, and will benefit from not
having to call binuptime(9) instead.

One problem with the CCNT register is that it is 32-bit only, so
the upper 32-bits of the returned number are always 0. The entropy
harvester does not care, but in case any one else does, follow-up
work may include an interrup trap to increment an upper-32-bit
counter on CCNT overflow.

Another problem is that the CCNT register is not readable in user-mode
code; in can be made readable by userland, but then it is also
writable, and so is a good chunk of the PMU system. For that reason,
the CCNT is not enabled for user-mode access in this commit.

Like the x86, there is one CCNT per core, so they don't all run in
perfect sync.

Reviewed by:	ian@ (an earlier version)
Tested by:	ian@ (same earlier version)
Committed from:	WANDBOARD-QUAD
2014-05-14 19:11:15 +00:00
Ruslan Bukin
876ac29ddc Fix typo. 2014-05-14 14:19:57 +00:00
Aleksandr Rybalko
279204f2e0 Remove extra newlines.
No functional changes.

Sponsored by:	The FreeBSD Foundation
2014-05-14 11:15:48 +00:00
Ian Lepore
ad622f7078 Cleanup some style nits. 2014-05-12 13:08:37 +00:00
Ian Lepore
02bb9ba1cc Interrupts need to be disabled on entry to cpu_sleep() for ARM. Given
that and the need to be in a critical section when switching to idleclock
mode for event timers, use spinlock_enter()/exit() to achieve both needs.

The ARM WFI (wait for interrupt) instruction blocks until an interrupt is
asserted, and it will unblock even if interrupts are masked, and it will
unblock immediately if an interrupt is already pending.  It is necessary
to execute it with interrupts disabled, otherwise the interrupt that
should unblock it may occur and be serviced just prior to executing the
instruction.  At that point the system is inappropriately asleep until
the next timer tick or some other random interrupt happens.

In general, interrupts need to be disabled continuously from the time the
decision is made that there is no work to be done and sleeping is needed
until actually going to sleep, to avoid a race where handling a new
interrupt changes the basis for deciding there is no work to be done.

Submitted by:	hps@ (in slightly different form)
2014-05-12 13:05:03 +00:00
Ian Lepore
b07d0cbce3 Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier().
On modern ARM SoCs the L2 cache controller sits between the CPU and the
AXI bus, and most on-chip memory-mapped devices are on the AXI bus.  We
map the device registers using the 'Device' memory attribute, which means
the memory is not cached, but writes to it are buffered.  Ensuring that a
write has made it all the way to a device may require that the L2
controller take some action.

There is currently only one implementation of the new function, for the
PL310 cache controller.  It invokes a function that the controller
manual calls "cache sync" but it actually has nothing to do with cache at
all, it triggers a drain of all pending store buffer writes and it blocks
until they complete.

The sheeva and xscale L2 controllers (which predate the concept of Device
memory) don't seem to have a corresponding function.  It appears that the
standard armv5 drain_writebuf function includes draining all the way
through the L2 controller.
2014-05-11 04:24:57 +00:00
Peter Grehan
ffd328487a Enable SMP for Exynos-based platforms (i.e. Chromebook)
Reviewed by:	br
2014-05-11 04:18:51 +00:00
Ian Lepore
6af0d51bce Make the hardware memory and instruction barrier functions work on armv4
and armv5 as well.
2014-05-11 00:43:06 +00:00
Andrew Turner
b36b897e51 Rename platform_gpio_init to be SoC specific 2014-05-10 21:30:19 +00:00
Andrew Turner
87ef4d1f85 Rename platform_gpio_init to be platform specific, and make it static as
it's only used from this file.
2014-05-10 20:31:05 +00:00
Andrew Turner
3664cbc0f0 Rename platform_gpio_init to be SoC specific, and make it static as it's
only called from this file.
2014-05-10 20:26:49 +00:00
Ian Lepore
b8821f8415 When mapping device memory, use PTE_DEVICE rather than PTE_NOCACHE.
On armv4 these are defined as synonyms right now, but it's a bit ambiguous
what NOCACHE means (is buffering/write-combining also enabled or not?); this
is a first step towards replacing PTE_NOCACHE with a less ambiguous name.
2014-05-10 20:03:03 +00:00
Ian Lepore
dfd03689d7 Call idcache_inv_all from the AP core entry code before turning on the MMU.
Also, enable instruction and branch caches, which should be safe now that
they're properly initialized/invalidated first.
2014-05-09 19:14:34 +00:00
Ganbold Tsagaankhuu
08d56ebf0a Add the codes for enabling CPU cores of Rockchip RK3188 SoC.
Enable SMP for Radxa Rock board.

Approved by:	stas (mentor)
2014-05-09 05:39:57 +00:00
Ian Lepore
9f8e153645 Consolitate all the AP core startup stuff under a single #ifdef SMP block.
Remove some other ifdefs that came in with a copy/paste that mean basically
"if this processor supports multicore stuff", because if you're starting up
an AP core... it does.
2014-05-08 20:02:38 +00:00
Ian Lepore
f296249f58 Move the mptramp code which is specific to the Marvell ArmadaXP SoC out of
the common locore.S file and into the mv/armadaxp directory.
2014-05-08 18:36:42 +00:00
Ian Lepore
0bd55d38ec Use edge-triggered interrupts rather than polling loops to avoid missing
transitions of the INIT_B line.  Also, release the mutex during uiomove().

Submitted by:	Thomas Skibo <ThomasSkibo@sbcglobal.net>
2014-05-08 17:20:45 +00:00
Ian Lepore
95da66135d Enable PL310 power-saving modes and tune the cache ram latencies for imx6. 2014-05-06 14:26:24 +00:00
Ian Lepore
334b9c79c3 Add a public routine to set the L2 cache ram latencies. This can be
called by platform init routines to fine-tune cache performance.
2014-05-06 14:19:54 +00:00
Ian Lepore
7b41388248 Add defines for the bits in the PL310 debug control register.
This should have been part of r265444.
2014-05-06 14:08:42 +00:00
Ian Lepore
b450e1090d Call platform_pl310_init() before enabling the controller, and handle the
case where the controller is already enabled.

Some of the pl310 configuration registers cannot be changed while the
controller is active, so if there is any platform-specific init to be done
it must happen before enabling the controller.

The controller should not be enabled upon entry to the kernel, but u-boot
has recently developed the bad habit of leaving caches enabled when
launching the kernel, and since we have no control over that source code
we have to do our best to cope with it.  The PL310 manual doesn't document
a safe sequence for disabling the controller, but the sequence used here
(force write-through mode and disable linefill allocations, then clean and
invalidate the current contents before disabling the hardware) appears to
be sound both by analysis and empirical testing.

These changes were developed and tested in collaboration with
Svatopluk Kraus <onwahe@gmail.com>.

Reviewed by:	cognet@
2014-05-06 14:03:35 +00:00
Ian Lepore
9925f09b81 Break out the code that figures out the L2 cache geometry to its own
routine, so that it can be called from multiple places in upcoming changes.
2014-05-06 13:46:36 +00:00
Ian Lepore
a787d4c699 Move the pl310.enabled tunable to hw.pl310.enabled. Clean up a few minor
style(9) nits.  Use DEVMETHOD_END.
2014-05-06 13:38:34 +00:00
Luiz Otavio O Souza
1deba728cd Fix the tinderbox armv6/arm build failure.
VYBRID code depends on FDT.
2014-05-03 03:40:36 +00:00
Ganbold Tsagaankhuu
b4ce42b4b8 Switch to use arm_devmap_add_entry() to setup static device mapping.
Approved by:	stas (mentor)
2014-05-02 01:20:13 +00:00
Warner Losh
9f06808398 This was copied to IMX6, which has since evolved further. Remove this
as it is no longer needed.
2014-04-30 18:02:19 +00:00
Warner Losh
7621eebbb1 Omit from the universe build all config files tagged with
#NO_UNIVERSE. Many of these config files are important examples, but
add little to no regresive value to the intended purpose of
UNIVERSE. We now build over 120 kernels during universe. There's
really little to no value to this over building say 60 or even 30 of
them (either is still a way too big number). This is especially true
for kernels that are nothing more than including a common base and
adding a static DTB file. Start by pruning 1/3 of the arm kernels that
add little regresion value.
2014-04-30 18:02:10 +00:00
Ian Lepore
4c05359867 Convert the Zynq SoC support to the new routines for static device mapping. 2014-04-30 14:38:13 +00:00
Ian Lepore
457e64a02f Make this declaration into a proper function prototype. 2014-04-29 23:29:28 +00:00
Ian Lepore
06177e52c9 Add SMP support for Zedboard.
Submitted by:	Thomas Skibo <ThomasSkibo@sbcglobal.net>
2014-04-29 17:48:57 +00:00
Ian Lepore
440fe55df6 Don't use multiprocessing-extensions instruction on processors that don't
support SMP.

Submitted by:	loos@
Pointy hat to:	me
2014-04-28 02:35:28 +00:00
Ian Lepore
88b3694bd9 Move duplicated code to print l2 cache config into the common code. 2014-04-27 23:47:38 +00:00
Ian Lepore
f62cbe0e49 Explain why wbinv_all is SMP-safe in this case, and add a missing l2 cache
flush.  (Either it was missing here, or it isn't needed in the minidump
case.  Adding it here seems like the safer path to consistancy.)
2014-04-27 20:26:15 +00:00
Ian Lepore
fa046341af Flush and invalidate caches on each CPU as part of handling IPI_STOP.
Flushing the caches is required before doing a panic dump, but ARM
doesn't provide a flavor of flush that gets broadcast to other cores.
However, all cores except one are stopped before doing a dump, so this
works around the lack of a global flush/invalidate by doing it locally
on each CPU as part of stopping.

Discussed with:	cognet@
2014-04-27 20:16:51 +00:00
Ian Lepore
824e4131a0 There is no difference between IPI_STOP and IPI_STOP_HARD on ARM, so
map them both to the same interrupt number like other arches do.
2014-04-27 20:01:59 +00:00
Ian Lepore
edecf7f6c1 Remove cpu_idcache_wbinv_all() from kdb_cpu_trap(), it's no longer needed.
This was added ca. 2004 for the purpose of ensuring the caches were in the
right state after the debugger set a breakpoint.  kdb_cpu_sync_icache()
was added in 2007 to handle that situation, and now the wbinv_all is
actually harmful because the operation isn't broadcast to other cores.
2014-04-27 18:12:55 +00:00
Ian Lepore
91c650065a Provide a proper armv7 implementation of icache_sync_all rather than
using armv7_idcache_wbinv_all, because wbinv_all doesn't broadcast the
operation to other cores.  In elf_cpu_load_file() use icache_sync_all()
and explain why it's needed (and why other sync operations aren't).

As part of doing this, all callers of cpu_icache_sync_all() were
inspected to ensure they weren't relying on the old side effect of
doing a wbinv_all along with the icache work.
2014-04-27 00:46:01 +00:00
Ian Lepore
75c95895f5 Call cpu_icache_sync_range() rather than sync_all since we know the range
and flushing the entire icache is needlessly expensive.
2014-04-26 23:09:01 +00:00
Scott Long
60ad8150c7 Retire smp_active. It was racey and caused demonstrated problems with
the cpufreq code.  Replace its use with smp_started.  There's at least
one userland tool that still looks at the kern.smp.active sysctl, so
preserve it but point it to smp_started as well.

Discussed with: peter, jhb
MFC after: 3 days
Obtained from: Netflix
2014-04-26 20:27:54 +00:00
Ian Lepore
a7fa939bb3 Stop calling imx51_ccm_foo() clock functions from imx6 code. Instead
define a few imx_ccm_foo() functions that are implemented by the imx51 or
imx6 ccm code.  Of course, the imx6 ccm code is still more a wish than
reality, so for now its implementations just return hard-coded numbers.
2014-04-26 16:48:09 +00:00