Commit Graph

803 Commits

Author SHA1 Message Date
Jayachandran C.
36a7e25854 PCIe updates for XLS.
Fix interrupt routing so that the irq returned is correct for XLR and
XLS. This also updates the MSI hack we had earlier - we still don't
really support MSI, but we support some drivers that use MSI, by providing
support for allocating one MSI per pci link - this MSI is directly
mapped to the link IRQ.
2010-09-07 07:31:58 +00:00
Jayachandran C.
3434740df2 Whitespace fixes - indent with tabs instead of spaces.
Few other style(9) changes.
2010-09-07 06:02:43 +00:00
Jayachandran C.
70b4737e05 On boards with >512MB memory, the result of vtophys cannot be converted
to KSEG1 address - use pmap_mapdev/pmap_unmapdev instead.

Remove unused variable maxphys.
2010-09-07 05:39:24 +00:00
Jayachandran C.
96001a35e1 XLR/XLS hardware interrupts should be programmed level triggered at the
PIC.  This should fix the interrupt releated issues seen after the
interrupt handling re-write for SMP.
2010-09-06 06:18:49 +00:00
Jayachandran C.
833182b77e Updates for the RMI MIPS platform code
- set cache_coherent_dma flag in cpuinfo for XLR, this will make sure that
  BUS_DMA_COHERENT flag is handled correctly in busdma_machdep.c
- iodi.c, call device_get_name() just once
- clear RMI specific EIRR while intializing CPUs
- remove debug print in intr_machdep.c
2010-09-01 17:35:31 +00:00
Jayachandran C.
55d308bc94 Add the workaround for 4xx lite boards after it was lost in the last
board.c update.
2010-08-31 04:18:47 +00:00
Jayachandran C.
79994806a1 Move debug.h to the the rge driver directory. rge.c is the only user of
debug.h. Remove debug.h references from other files.
2010-08-30 13:26:07 +00:00
Jayachandran C.
61b993a34f Clean up header files in RMI platform code (sys/mips/rmi), and remove
unused files.

- remove clock.c and clock.h, these are not used after the new timer
  code was added.
- remove duplicated include files, fix header file ordering, remove
  some unneeded includes.
- rename mips/rmi/shared_structs.h which contains the RMI boot loader
  interface to mips/rmi/rmi_boot_info.h. Remove unused files
  mips/rmi/shared_structs_func.h and sys/mips/rmi/shared_structs_offsets.h
- merge mips/rmi/xlrconfig.h and mips/rmi/rmi_mips_exts.h, and remove
  duplicated functions.
- nlge - minor change to remove unneeded argument.
- Add FreeBSD svn keyword for headers
2010-08-30 13:05:21 +00:00
Jayachandran C.
f936972752 Remove misleading comment in pte.h. MIPS PTE entries are software managed
and does not need atomics.

Submitted by:	alc
2010-08-30 08:23:22 +00:00
Jayachandran C.
9ebbcfd58b Apply MIPS pmap clean up patch from alc@ (with minor change to KASSERT):
PMAP_DIAGNOSTIC was eliminated from amd64/i386, and, in fact, the
  non-MIPS parts of the kernel, several years ago.  Any of the interesting
  checks were turned into KASSERT()s.  Basically, the motivation was that
  lots of people run with INVARIANTS but no one runs with DIAGNOSTIC.

  panic strings needn't and shouldn't have a terminating newline.

  Finally, there is one functional change.  The sched_pin() in
  pmap_remove_pages() is an artifact of the way we temporarily map page
  table pages on i386.  (The mappings are processor private.  We don't do
  a system-wide shootdown.)  It isn't needed by MIPS.

Tested by: jchandra

Submitted by:	alc
2010-08-29 05:39:21 +00:00
Jayachandran C.
d12f1e190e New driver nlge for XLR/XLS Network Accelerator. This will support the XGMAC
and XAUI 10G interfaces in addition RGMII/SGMII 1G interfaces.  This driver
is work in progress.

board.c and board.h expanded to include more info.

Only one of rge and nlge can be enabled at a time, rge will be deprecated
when nlge stabilizes.

Submitted by:	Sriram Gorti <srgorti at netlogicmicro com>
2010-08-28 19:02:51 +00:00
Jayachandran C.
97f047a80b Initial code for XLR CompactFlash driver.
Submitted by:	Sreekanth M. S. <kanthms at netlogicmicro com>
2010-08-28 07:58:10 +00:00
Jayachandran C.
b47f51b4a0 Revamp XLR interrupt handling, the previous scheme does not work well on
SMP.

We used to route all PIC based interrupts to cpu 0, and used the per-CPU
interrupt mask to enable/disable interrupts. But the interrupt threads can
run on any cpu on SMP, and the interrupt thread will re-enable the interrupts
on the CPU it runs on when it is done, and not on cpu0 where the PIC will
still send interrupts to.

The fix is move the disable/enable for PIC based interrupts to PIC, we will
ack on PIC only when the interrupt thread is done, and we do not use the
per-CPU interrupt mask.

The changes also introduce a way for subsystems to add a function that
will be called to clear the interrupt on the subsystem. Currently This is
used by the PCI/PCIe for doing additional work during the interrupt
handling.
2010-08-27 19:53:57 +00:00
Jayachandran C.
37b3715cdb Whitespace fixes in mips/include, remove unused 'struct tlb' from locore.h
PR:		misc/147471
2010-08-27 07:45:50 +00:00
Jayachandran C.
867a12afe1 Provide timecounter based on XLR PIC timer.
- Use timer 7 in XLR PIC as a 32 counter
- provide pic_init_timer(), pic_set_timer(), pic_timer_count32() and
  pic_timer_count() PIC timer operations.
- register this timer as platform_timecounter on rmi platform.
2010-08-25 13:37:55 +00:00
Jayachandran C.
f6f7fc21c4 XLR PIC code update.
- Fix a bug in xlr_pic_init (use irq in PIC_IRQ_IS_EDGE_TRIGGERED)
- use new macro PIC_INTR_TO_IRQ() and PIC_IRT_x() in xlr_pic_init
2010-08-25 12:10:20 +00:00
Jayachandran C.
30eb8eda72 XLR PIC code update and style(9) fixes.
- style(9) fixes to mips/rmi platform files
- update pic.h to add pic_setup_intr() and use pic_setup_intr() for setting
  up interrupts which are routed thru PIC.
- remove rmi_spin_mutex_safe and haslock, and make sure that the functions
  are called only after mutexes are available.
2010-08-25 11:49:48 +00:00
Jayachandran C.
afc1e71002 Rename on_chip.c to fmn.c, as the file has just the fast messaging network
code.  The iodi.c has the bus for SoC devices, so the name on_chip.c is
misleading.
2010-08-25 09:53:00 +00:00
Jayachandran C.
5cdefefaed RMI XLR platform code clean-up.
- move PIC code to xlr_machdep.c
- move fast message ring code completely to on_chip.c
- move memory initialization to a new function xlr_mem_init()
- style fixes
2010-08-25 08:48:54 +00:00
Jayachandran C.
871726d7e9 Sync up XLR tick.c with the new MIPS tick.c 2010-08-25 07:33:35 +00:00
Adrian Chadd
813b73a5a9 Migrate if_arge to use the PLL cpuops.
This has been lightly tested on the AR7161 and AR9132.
2010-08-19 16:29:08 +00:00
Adrian Chadd
303fea5cdc Implement PLL generalisation in preparation for use in if_arge.
* Add a function to write to the relevant PLL register
* Break out the PLL configuration for the AR71XX into the CPU ops,
  lifted from if_arge.c.
* Add the AR91XX PLL configuration ops, using the AR91XX register
  definitions.
2010-08-19 16:25:15 +00:00
Adrian Chadd
44c5dea1d8 add the PLL set functions to cpuops 2010-08-19 16:15:30 +00:00
Adrian Chadd
88e08e7ce6 Fix mistaken indenting. 2010-08-19 12:52:49 +00:00
Adrian Chadd
c4df93502d Add some initial AR724X chipset support.
This is untested but should at least allow an AR724X to boot.

The current code is lacking the detail needed to expose the PCIe bus.
It is also lacking any NIC, PLL or flush/WB code.
2010-08-19 11:53:55 +00:00
Adrian Chadd
f3135331c6 Add initial Atheros AR91XX support.
This works well enough to bring a system up to single-user mode
using an MDROOT.

Known Issues:

* The EHCI USB doesn't currently work and will panic the kernel during
  attach.
* The onboard ethernet won't work until the PLL routines have been
  fleshed out and shoe-horned into if_arge.
* The WMAC device glue (and quite likely the if_ath support)
  hasn't yet been implemented.
2010-08-19 11:40:10 +00:00
Adrian Chadd
c2ddd1eef7 Add missing licence. 2010-08-19 11:18:50 +00:00
Adrian Chadd
8d19ed7cbc style(9) pick from imp@ . 2010-08-19 11:16:52 +00:00
Adrian Chadd
292899c376 Remove now unused 'reg'. 2010-08-19 02:15:39 +00:00
Adrian Chadd
6f96ebf309 Initialise the USB system using cpuops rather than the AR71XX specific method. 2010-08-19 02:14:53 +00:00
Adrian Chadd
1d11005672 Migrate the CPU reset path to use the new cpuops. 2010-08-19 02:12:04 +00:00
Adrian Chadd
5b877d30b5 Remove the now-unused DDR flush register value. 2010-08-19 02:10:05 +00:00
Adrian Chadd
23f10186b5 Make the PCI initialisation path use the new cpuops rather than directly
programming the reset register.
2010-08-19 02:05:16 +00:00
Adrian Chadd
fd11fd075a Make if_arge use the new cpuops rather than hard coding the DDR flush registers. 2010-08-19 02:04:35 +00:00
Adrian Chadd
70bd9230d1 Preparation work for supporting the AR91xx and AR724x.
* Implement a SoC probe function, from Linux, which determines the
  SoC family, type and revision. This only probes the AR71xx series
  SoC and (currently) panics on others.

* Migrate some of the AR71XX specific hardware init (USB device, determining
  system frequencies) into using the cpuops introduced in an earlier commit.
  Other SoC specific hardware stuff (per-device flush/WB, GPIO pin wiring,
  Ethernet PLL setup, other things I've likely missed) will be introduced in
  subsequent commits.

Reviewed by:	imp@
Obtained from:	(partially) Linux
2010-08-19 02:03:12 +00:00
Jayachandran C.
8eec5e8f9c MIPS n64 support - continued...
1. On n64, use XKPHYS to map page table pages instead of KSEG0. Maintain
   just one freepages list on n64.

   The changes are mainly to introduce MIPS_PHYS_TO_DIRECT(pa),
   MIPS_DIRECT_TO_PHYS(), which will use KSEG0 in 32 bit compilation
   and XKPHYS in 64 bit compilation.

2. Change macro based PMAP_LMEM_MAP1(), PMAP_LMEM_MAP2(), PMAP_LMEM_UNMAP()
  to inline functions.

3. Introduce MIPS_DIRECT_MAPPABLE(pa), which will further reduce the cases
   in which we will need to have a special case for 64 bit compilation.

4. Update CP0 hazard definitions for CPU_RMI - the cpu does not need any
   nops

Reviewed by:	neel
2010-08-18 12:52:21 +00:00
Adrian Chadd
5429211e0a Add a DDR flush function, inspired by both Linux and if_arge.c. 2010-08-18 09:11:45 +00:00
Adrian Chadd
3692b33ce3 Add a further register definition for USB device initialisation.
Obtained from:	Linux
2010-08-18 08:22:58 +00:00
Adrian Chadd
4d843b15ca Bring over the first cut of the Atheros-specific SoC operations.
Each of these SoCs have different devices, different hardware initialisation
methods and, quite likely, different quirks. These functions will abstract
out the SoC differences and keep these differences out of the drivers (eg
USB init, if_arge, etc.)
2010-08-18 08:22:09 +00:00
Jayachandran C.
e792023fe1 Make return statements style(9) compliant in MIPS pmap.c
Reported by: neel

Reviewed by:	neel (earlier version)
2010-08-18 07:38:13 +00:00
Adrian Chadd
7f8184068f Import initial AR91XX and AR724X CPU register definitions.
Obtained from:	Linux
2010-08-18 00:26:14 +00:00
Konstantin Belousov
ee235befcb Supply some useful information to the started image using ELF aux vectors.
In particular, provide pagesize and pagesizes array, the canary value
for SSP use, number of host CPUs and osreldate.

Tested by:	marius (sparc64)
MFC after:	1 month
2010-08-17 08:55:45 +00:00
Jayachandran C.
a7834bac09 Rename TARGET_XLR_XLS to CPU_RMI to match other CPU_xxx definitions.
use CPU_RMI all XLR configurations. Update ident string for N32 and
N64 kernels.
2010-08-13 12:56:00 +00:00
Jayachandran C.
e5295c2487 SMP support in n64.
- Enable KX and UX bits on CPU startup for non-boot CPUs
- Keep the KX bit when in userspace - XTLB handler needs it to access
  PCPU data
- revert r210638 partly - we don't need to enable KX on kernel entry
  now

Reviewed by:	jmallett, imp
2010-08-12 11:00:45 +00:00
Jayachandran C.
619fede20e Implement pmap changes suggested by alc@:
1. Move dirty bit emulation code that is duplicted for kernel and user
in trap.c to a function pmap_emulate_modified() in pmap.c.

2. While doing dirty bit emulation, it is not necessary to update the
TLB entry on all CPUs using smp_rendezvous(), we can just update the
TLB entry on the current CPU, and let the other CPUs update their TLB
entry lazily if they get an exception.

Reviewed by:	alc, neel
2010-08-12 10:09:28 +00:00
Jayachandran C.
b47b62ea82 Optimization for pmap_kenter(), call pmap_update_page() only when
necessary.  On SMP, pmap_update_page() can be costly as it needs a
a smp_rendezvous().

Reviewed by:	alc, neel
Obtained from:	jmallett (http://svn.freebsd.org/base/user/jmallett/octeon)
2010-08-12 09:15:27 +00:00
Jayachandran C.
4bbc34b56e Re-arrange the pmap calls that use smp_rendezvous() on SMP, so that their
per-cpu variants are also available to be called.  The per-cpu variants
are needed for some later optimizations.

Also remove unnecessary casts, do some style fixes.

Reviewed by:	alc, neel
2010-08-12 09:03:21 +00:00
John Baldwin
60c7b36b7a Update various places that store or manipulate CPU masks to use cpumask_t
instead of int or u_int.  Since cpumask_t is currently u_int on all
platforms this should just be a cosmetic change.
2010-08-11 23:22:53 +00:00
Jayachandran C.
0a2a21691c Fix for 64 bit compile, with SMP enabled. 2010-08-11 19:56:09 +00:00
Jayachandran C.
643e9900ec Fix compilation when DDB disabled. Adds 'ifdef DDB' around
DB_SHOW_COMMAND definitions.
2010-08-11 06:43:14 +00:00