interrupt for the CSC interrupt, then we revert to ISA. If we didn't
have an interrupt set up with hw.pcic.irq, then do polling.
Also, don't complain about ignoring function 1 for any devices except
pcic devices. This would normally only show up if someone set
hw.pcic.ignore_function_1=1.
MFC: as soon as I can test it on some troublesome laptops.
explain the subtle side effects that are going to happen and why we go
ahead and ack the interrupt source. This stuff is tricky to get
right.
Also, emperical tests have shown that doing a shutdown in attach to be
ineffectual, so remove it from there. Analysis of the code paths
shows that nearly identical writes to these registers happen in later
parts of the code. The hanging problem on thinkpads when we change
the interrupt routing type is something else.
shutdown and also before we get going with the device initialization.
This may fix the hangs some people are seeing on warmboot. It appears
that some machines will reset the cardbus bridge on boot, while others
don't. So we turn off the card, and ack the interrupts (which likely
is a nop in the shutdown case since we're still fielding interrupts).
This should turn off the interrupts.
Since I don't have hardware that hangs on reboot, I'm committing this
without testing that aspect of the patch (it causes no harm on my
Dell).
initialization structure. Warn the user for those chipsets that
aren't yet customized that they might not work. Second, try to power
off the slot on attach and ack the interrupts. I don't know, but this
might solve the hangs that people will see on Thinkpads if they set
hw.pcic.init_routing=1.
request and just calling it when we get a bridge interrupt. The
problem is that if other code wants to block hardware interrupts for a
little bit with splXXX, those masks aren't updated the way we're doing
it. This doesn't matter for -current, but does for -stable.
The whole reason that we were catching interrupts was to detect that
the card was still there. Ian's fixes however ensure that the card
will be there with an interrupt handler, or not there at all. Since
the pcic interrupt is at a high priority, this should be OK.
This should fix the network related crashes people started seeing in
stable after I merged the pcic as a pci device code.
Submitted indirectly by: Ian Dowse
MFC when: Ian has had a chance to do his torture hang testing.
the ISR. We keep track of the card state and don't call the IRS when
the card isn't inserted. This helps quite a bit with card ejection
problems that Ian was seeing.
Submitted by: Ian Dowse
MFC upon: re approvel.
assing an IRQ. Add better comments while I'm here.
MFC after: 1 day
# Note: That's merging all the -current pci pcic code, not just this one
# change for the Aug 15th code freeze.
register. It enables Zoom Video. It appears that on at least one
card that Monzoon is using sets these bits by default. Nothing works
when these bits are set, everything works when they are clear.
Add commentary on some of the ti bits. Make code a little clearer.
Also remove a call to pcic_pci_pd6729 which was prematurely added in
the last commit.
can't blindly write zero into it to disable the card. We must
preserve this bit. This changes pcic_disable to only clear the bits
we know we need to clear on card disable, thus preserving the magic
bit for many TI bridges.
This appears to have fixed the problems that people are reporting
about the system failing to recognize cards being inserted or removed
(or both). Greg: This may fix your problem too :-).
is the diagnostics register at offset 0x93. When bit 5 is set in this
register, bits 4-7 in ExCA register 0x5 being 0000 are required for
pci interrupt routing. When it is clear, then bit 4 of ExCA register
0x3 is used to enable it.
The only other issue is that when you route interrupts this way, you
must read ExCA register 0x4 in order to clear the interrupt, else you
get an interrupt storm.
Deal with this requirement by setting things up. It is believed that
this won't hurt other chipsets, but other chipsets may require their
own work arounds.
o Move PIOCSRESOURCE from pccard to pcic so the kernel can give pccardd
better hints as to what resources to use.
o Implement an undocumented hw.pcic.interrupt_route to allow people that
need to do so to route their interrupts in a non-standard way.
o Only preallocate a resource in probe if we're routing via pci.
o If we aren't routing via pci, then set the irq to use explicitly
to defeat the automatic IRQ routing of the pci layer.
This, with the pccardd code should be close to what can be committed
to -stable.
resources it is attempting to assign to a child object. This should
help people track down mysterious resource allocation problems more
easily.
# Unfortunately, it is harder to do the conflict check and report which
# resource failed if the driver itself doesn't.
strictly necessary on current, but having it in here makes the diffs with
stable smaller and doesn't hurt anything except for phk's redundant include
finder.
hw.pcic.irq Globally set the IRQ for all pcic devices' management
interrupt (aka card status change or CSC interrupt)
This is what used to be known as
machdep.pccard.pcic_irq (which has been retained for
now for compatibility).
hw.pcic.ignore_fuction_1 Ignores function 1 for all PCIC bridges by not
attaching to them. Lucent released a huge batch
of cards that were imporperly manufactuered (lacking
the 0 ohm resister to disable slot 1). This is
a big hammer to keep those cards from causing problems
(I've had 4 people contact me saying my patches
worked great once they added a kludge to always ignore
function 1, or until they soldered these resistors
in place!).
No clue where to document these. They act as both boot loader environment
variables, as well as read-only sysctls after boot.
At the same time, sort sys/systm.h in its proper order after sys/sysctl.h.
o kill blank line that I introduced in cardinfo.h
o Delete unused variable wasinactive.
o return 0 from pccard_resume.
o Set the state and lastsate initially to be empty.
o move comment above code for interrupt dispatching.
o Powerstate interface is now available as of 430002, not 500000 (note that
this change will be not 100% correct since the power state stuff didn't
enter current until well after 500000, but it is good enough for the two
branche we have going now).
power x 0.
pccardc power x 0 used to disable the slot. But a suspend/resume
would reactivate the pccard. It no longer does that. Now the
disabling of the slot is sticy until it is reset with power x 1 or the
card is ejected. This seems closer to correct behavior to me.
o Process all card state changes the same using pccard_do_stat_change().
o Cleanup disabling the card so that we can preserve the state after
the change. Basically, don't set it to empty as often as we do.
o On suspend, the new state is "empty" and the laststate is "suspend"
o Document state machine with a diagram of states and edges. The
edges are labeld to tell the reader what event causes the external
state changes.
o "machdep.pccard.pcic_resume_reset" may be obsolete now. We always
call the bridge driver's resume method on resume now. Otherwise cards
won't automatically show up. If it needs to stay, I'll add it back.
longer have a pccard in the slot. This fixes the problem where pccard
would say that a card had been inserted on resume. This also appears
to make the insert/remove events more reliable after a resume as well,
but that may be a different bug I need to hunt down.
Sometimes, when pccardd is restarted, it fails to realize that the
device is already attached and tries to attach it again. This leads
to bad mojo since the pccard code isn't setup to handle that, so the
panic was put in. Now it appears that it is triggering too easily, so
I'm backing it off to a non-fatal error.
Frist, for pci slots, make the setup intr save the requested interrupt
vector and arg and return rather than passing it up to our parent. On
interrupts, we call this vector iff there's a card in the slot. This
should eliminate some of the hangs or "weird" messages that people see
when ejecting cards and also help close the race window somewhat.
Reading the pci bus one more time for this information is judged to be
an acceptible tradeoff since it is very very fast.
Cleanup a little how we detect unsupported cards. Only detect
unsupported cards (eg cardbus cards) on card insertion (or more
pedantically when a card is actually present). This should allow us
to change the message in the future to "cardbus card not supported
with OLDCARD" :-).
Note:
We may also consider this for the ISA bus case, but there the
reads are much more expensive and the location of the CD pin
status lines appears to be less standardized. Also, the ISA
management interrupt isn't shared with the card's interrupt.
The mutliplex the CSC and function interrupts bit also appears
to be non-standard (or at least not imlemented on all
bridges).
because NEWBUS (and I think some versions of Windows sometimes) writes
0xffffffff to these registers to disable them. When they are
"disabled" like this, writing memory ranges to the pcic registers are
ignored and you will get "card (null) (null)" when you insert a call
otherwise.
each of the bridge chips. Before we wrongly assumes that all cardbus
bridge chips were intel compatible step A/B. This mostly worked, but
likely caused problems with certain cirrus logic cardbus bridges.
rejecting INTR_FAST interrupts. Since they can't be shared anyway,
this just short circuits a failure case that should work but is panic
fodder now.
This bug is that if the interrut condiation is active when you activate
the interrupt, then the interrupt routine will be called. jhb had
a patch that may or may not work to fix it, but I've lost it.
This may be due to the sio probe doing something odd too.
information until the problems can be tracked down. Right now these
are unconditional, but later it will be hidden behind a boot verbose.
Also, if there are no events listed in the event mask, return right
away. Specifically avoid writing back interrupt acks in this case.
Print type of pci bridge we find.
Force the IRQ of pci bridges upon all its children.
Allocate the resources on behalf of the bridge when we're testing to see if
they exist.
This should help people who don't read updating instructions very well.
This patch started out with an idea from Shigeru Yamamoto-san in -current.
told to use IRQ 6, progam the pcic to use irq 7 instead. Evidentally,
at least some of the cards are wired this way. If you want to use irq
6, configure it. All the mapping is done just before we set the
interrupt registers. See [FreeBSD98-testers 5064] for details.
Added commentary about valid interrupts on some CBUS pc98 CL PD6722
based cards.
Submitted by: Hiroshi TSUKADA-san <hiroshi@kiwi.ne.jp>
higher chips. Treat it as if it were a 113x. This is correct as far
as 16-bit cards go, at least how we're using it.
# It appears that my TI-1031 based pci card that YAMAMOTO shigeru-san gave
# me on my trip to Japan now works.
elected to do this in the probe rather than the attach so that we don't
disturb things which this might reset. different cards have different
quirks, according to their datasheets.
This should fix the "I booted in windows and rebooted to FreeBSD and
now things don't work" problem.
PR: 4847, 20670
card bus bridges.
We now always use pci interrupts for pci cards. This will allow us to
more easily configure things. You must change your IRQ lines in
/etc/pccard.conf to match what we've probed. I'm not sure the right
way to deal with this right now.
Development of pci pcmcia has been funded by Monzoon Networks AG. I
am grateful for their generosity.
for card change interrupts is different than the pci stuff that's
coming soon. Set the management irq in different ways. If
pci_parallel interrutp routing, then use the PCI way of getting
interrupts. Move polling mode into pcic_isa since when we're routing
via pci polling doesn't work because many bridges (systems hang solid).
If we're routing interrupts via pci, they can be shared, so flag them
as such.
Note, this doesn't actually change anything since the pci attachment
isn't quite ready to be committed.
csc_route and func_route to hold the way that each interrupt is
routed. csc is Card Status Change in the datasheets and standard, but
is called "Management Interrupt" in FreeBSDese. There are three types
of interrupt routing: ISA parallel, PCI parallel and ISA serial (some
chipsets support other types as well, but I don't plan on supporting
them).
When we try to allocate an interrupt, and the type for that interrupt
is pci_parallel, allow it to be shared by oring in RF_SHAREABLE to the
flags argument. Introduce pcic_alloc_resource to allow this to
happen.
interrupts on other buses. Right now it isn't used, but will be for
the pci attachment.
# Add copyright by me for this year since I've changed so much.
o If the class is PCIC_BRIDGE, subclass is PCIS_BRIDGE_PCMCIA and
programming interface is 0, assume that it is a generic PCMCIA PCI
chip we can program. I don't think there are any of these that
we don't know about, but you never know.
o If the class is PCIC_BRIDGE, subclass is PCIS_BRIDGE_CARDBUS and
programming interface is 0, assume that it is a YENTA cardbus bridge
that we know how to cope with. There are likely some cardbus bridges
that haven't it made it in here yet.
pcic_{get,put}b_io. There are some pci bridges (the CL-PD6729 and
maybe others) that do not have memory mapped registers, so we'll need
these in both places. Declare them in pcicvar.h.
have a slightly different 3.3V support than the other clones, so
compensate as best we can. Note: 3.3V support is untested since I do
not have any 3.3V cards that I know of to test it with.
Work through the various power commands and convert them from a "is
this a foo controller or a foo' controller or a foo''' controller" to
a cabability based scheme. We have bits in the softc that tell us
what kind of power control scheme the controller uses, rather than
relying on being able to enumerate them all. Cardbus bridges are
numerous, but nearly all implement the i82365sl-DF scheme (well, a few
implement cirrus CL-PD67xx, but those were made by Cirrus Logic!).
Add a pointer back to the softc in each pcic_slot so we can access
these flags.
Add comments that talk about the issues here. Also note in passing
that there are two differ Vpp schemes in use and that we may need to
adjust the code to deal with both of them. Note why it usually works
now.
We have 5 power management modes right now: KING, AB, DF, PD and VG.
AB is for the i82365 stpes A, B and C. DF is for step DF. PD is the
cirrus logic extensions for 3.3V while VG is the VADEM extensions for
3.3V. KING is for the IBM KING controller found on some old cards.
# I'm looking for one of those old cards or a laptop that has the KING
# bridge in it.
We have to still cheat and treat the AB parts like the DF parts
because pci isn't here yet. As far as I can tell, this is harmless
for actual old parts and necessary to work with 3.3V cards in some
laptops.
This almost eliminates all tests for controller in the code. There
are still a few unrelated to power that need taming as well.
o Introduce flags word to the softc. This will be used to control various
aspects of the driver. Right now there are two bits defined, PCIC_IO_MAPPED
and PCIC_MEM_MAPPED. One for ISA cards that are I/O mapped, the other is
for PCI cards that are memory mapped. Only the ISA side is implemented
with this commit.
o Introduce a pcic_dealloc which will cleanly dealloc resources used. Right
now it is only supported when called from probe/attach.
o Keep track of resources allocated in the pcic_softc.
o move pcictimeout_ch to the softc so we can support multiple devices
in polling mode.
o In ISA probe, set PCIC_IO_MAPPED.
o Introduce and compute the slot mask. This will be used later when
we expand the number of slots on ISA from 2 to 4. In such a case, we
appear to have to use polling mode otherwise we get two different cards
trying to drive the same interrupt line. I don't have hardware to
test this configuration, so I'll stop here.
o Add defines for the VS[12]# bits in register 0x16.
o Add comment about what we're doing reading register 0x16 (PCIC_CDGC)
in the DF case.
o Check bit VS1# rather than a random bit I was checking due to a bogus
transcrition on my part from nakagawa-san's article.
o Add note about IBM KING and 3.3V operation from information larned from
wildboard.
things to get 3.3V. It appears that some cardbus chipsets have id
registers that say they are C step parts, but they really support the
DF step 3.3V functionality.
# Need to verify that IBM KING is handled properly since the MISC1
# register is really a cirrus logic only register.
82C146. The Intel i82365SL-DF supports 3.3V cards. The Step A/B/C
parts do not appear to support this. This is hard to know for sure
since it was deduced from "compatible" parts' data sheets and the
article mentioned below.
Rework the VLSI detection to be a little nicer and not depend on
scanning cards twice. This would allow bad VLSI cards to coexist with
a good intel card, for example. We now detect i82365SL-DF cards where
before we'd detect a VLSI. For the most part, this is good, but we
run a small chance of detecting a single slot 82C146 as a i82365SL-DF.
Since I can't find a datasheet for the 82c146, I don't know if this is
a problem or not.
This work is based on an excellent article, in Japanese, by NAKAGAWA,
Yoshihisa-san that appeared in FreeBSD Press Number 4. He provided a
patch against PAO3 in his article. Since the pcic.c code has changed
some since then, I've gone ahead and cleaned up his patch somewhat and
changed how the code detects the buggy '146 cards.
I also removed the comment asking if there were other cards that
matched the 82C146 since we found one and additional information isn't
necessary.
soon attach directly to pcic rather than the kludge pci-pcic device we
have now.
In some ways, this is similar to the work PAO3 did to try to support
cardbus bridges. In some ways different. This and future commits
will be taking from the spirit of many of those changes. pcicvar.h is
completely different from the pcicvar.h that appeared in PAO3, but
similar in concept.
controller found in many of the early NOTE98 machines that were
produced. This controller is completely unlike the intel 82365, so
I've separated it out from the main pcic driver.
