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189 Commits

Author SHA1 Message Date
Robert Noland
87c73f89a9 Add support for Radeon HD 4770 (RV740) chips. 
Approved by:	re@ (kib)
MFC after:	3 days
 2009-07-09 16:39:28 +00:00
Robert Noland
3db57ca311 We shouldn't need to drop and reaquire the lock here. 
MFC after:	3 days
 2009-06-25 19:23:25 +00:00
Robert Noland
a84a56f28b Some more cleanups for vblank code on Intel. 
The Intel 2d driver calls modeset before reinstalling the handler on
a vt switch.  This means that vblank status ends up getting cleared
after it has been setup.  Restore saved values for the pipestat registers
rather than just wiping them out.

MFC after:	3 days
 2009-06-25 18:27:08 +00:00
Robert Noland
a2cc8f993b Initialize max_vblank_count earlier. 
Small cleanup of the error paths while I'm here.

MFC after:	3 days
 2009-06-25 16:17:07 +00:00
Robert Noland
2642e635f2 Keep track of the hardware counter more aggressively while interrupts 
are enabled.  This should help to reduce cases where the hardware
counter reference jumps by large amounts.

MFC after:	3 days
 2009-06-25 15:47:32 +00:00
Robert Noland
a429bdf087 Fix one use of atomic for refcount missed in last commit. 
MFC after:	3 days
 2009-06-25 15:36:11 +00:00
Robert Noland
1f3c8cf88f Additional vblank cleanups. 
Use the vbl_lock when maniputlating the refcount.  Eventually I want to
convert this to use our internal refcount code.  Continue to use atomic
ops for manipulating vblank count since we access it often just for
reading.

MFC after:	3 days
 2009-06-25 15:30:25 +00:00
Robert Noland
a708803975 Ensure that we always hold the lock when calling vblank_disable_fn() 
MFC after:	3 days
 2009-06-25 14:15:45 +00:00
Robert Noland
abcd328be6 Add some sysctl info so that we can see what is going on with vblanks. 
MFC after:	3 days
 2009-06-23 20:19:02 +00:00
Robert Noland
128512d705 Only release irq resources if we were actually using them. 
MFC after:	3 days
 2009-06-23 18:24:09 +00:00
Robert Noland
179ab71fdd Using signals for vblank events is prone to issues. There have never 
been any consumers and likely will never be.  Furthermore, we have
never enabled the code for it, so just get rid of it.

MFC after:	3 days
 2009-06-23 18:09:35 +00:00
Robert Noland
a2d33c4900 Given that vblanks generally occur 60 times a second, waiting 3 seconds 
seems rather excessive.

MFC after:	3 days
 2009-06-23 17:52:41 +00:00
Robert Noland
3a5185e13a vblank[crtc].last represents the hardware counter while request.sequence 
represents the software counter.  Don't currupt things here.

MFC after:	3 days
 2009-06-23 17:50:35 +00:00
Robert Noland
5880b860f8 Hold the lock while we save/restore register for suspend/resume. 
MFC after:	3 days
 2009-06-23 17:38:28 +00:00
Robert Noland
e23637d17b The G45 docs indicate that all G4X chips use the new framecount register. 
Intel agrees with my reading of the docs, make it so for all G4X chips.

The new register also has a 32 bit width as opposed to 24 bits.  Fix
things up so that the counters roll over properly.

MFC after:	3 days
 2009-06-20 16:45:14 +00:00
Robert Noland
e8ca7a9956 realloc() behaves identically to malloc when passed a NULL object pointer 
If an error does occur we would have left max_context with an incorrect
value.

MFC after:	3 days
 2009-06-20 16:40:48 +00:00
Robert Noland
4949d88192 Don't panic if drm_rmmap is called with a NULL map pointer. 
MFC after:	3 days
 2009-06-20 16:37:24 +00:00
Robert Noland
8f6d3bf7a2 Don't try to setup interrupts for drivers that don't support them. 
This causes sis and probably a couple of other driver to panic and fail.

Tested by:	cpghost <cpghost@cordula.ws>
PR:		133554
MFC after:	3 days
 2009-04-19 16:54:33 +00:00
Robert Noland
e12ce94f36 check offsets for R300_ZB_ZPASS_ADDR 
Submitted by:	Maciej Cencora <m.cencora@gmail.com>
MFC after:	3 days
 2009-04-07 22:26:53 +00:00
Robert Noland
3c834e3435 Add regs required for occlusion queries support 
Submitted by:	Maciej Cencora <m.cencora@gmail.com>
MFC after:	3 days
 2009-04-07 22:20:58 +00:00
Robert Noland
27b31641fb Add support for RV790 (HD 4890) asics 
MFC after:	3 days
 2009-04-03 19:23:14 +00:00
Robert Noland
47c63e764d A little more cleanup from AMD, if we don't have the right microcode 
there is no reason to mess with the chip.

MFC after:	3 days
 2009-04-03 19:21:39 +00:00
Robert Noland
0351ecf9e4 Simplify the radeon microcode loading. 
Submitted by:	Christoph Mallon
MFC after:	3 days
 2009-03-31 17:52:05 +00:00
Robert Noland
221478e4c6 We don't know what these pages are going to be used for, they should be 
un-cached.  This got lost somewhere with all the bus_dma fixups.

MFC after:	3 days
 2009-03-30 18:01:42 +00:00
Robert Noland
04edf5eaf1 Load the right microcode for RS780. 
MFC after:	3 days
 2009-03-30 17:49:21 +00:00
Robert Noland
b0f6d6b6bb Fix up waiting on vblank again... This reverts a last minute change that 
I made on the last patch, it seems to upset suspend/resume and shutdown.

MFC after:	3 days
 2009-03-26 02:10:18 +00:00
Robert Noland
24c6d24b27 Rework the management of vblank interrupts a bit. 
When a vt switch occurs the irq handler is uninstalled.  Interrupts
and the state tracking of what was enabled/disabled wasn't working
properly.  This should resolve the reports of "slow windows" after a
vt switch, among other things.  The radeon 2d driver seems to work a
bit more correctly than the Intel driver.  With the Intel driver,
vblank interrupts will be enabled at system startup and will only
be disabled after an additional modeset (vt switch, dpms, randr event).

With this patch, I am able to run glxgears synced to vblank and
vt switch while it is running without ill effects.

MFC after:	3 days
 2009-03-25 01:50:56 +00:00
Robert Noland
a13575a303 Intel handled the management of the breadcrumb counter inconsistently. 
Make sure that we always handle it the same way.

MFC after:	3 days
 2009-03-25 01:44:16 +00:00
Robert Noland
eccb3bb8f6 The GART allocations are a propery of the gart, not of scatter-gather 
memory.  Track them in the appropriate structure.

MFC after:	3 days
 2009-03-25 01:41:56 +00:00
Robert Noland
746871c800 Fix up the flags to bus_dmamem again. The man page incorrectly showed 
the BUS_DMA_NOCACHE flags as being a valid flag for load instead of alloc.

Discussed with:	kib
MFC after:	3 days
 2009-03-22 20:58:29 +00:00
Robert Noland
a80ca4341a vm_offset_t is unsigned, so compare of >= 0 is not needed. 
Found with:	Coverity Prevent(tm)
CID:		2259

MFC after:	3 days
 2009-03-20 18:35:16 +00:00
Robert Noland
0bbcd5ca68 Remove the DRM_ERROR to fix build. It didn't make any sense anyway. 
MFC after:	3 days
 2009-03-20 18:01:32 +00:00
Robert Noland
c8264c8ee2 Fix what appears to be a typo, and restore the registers correctly. 
Found with:	Coverity Prevent(tm)
CID: 		2454
 2009-03-20 17:51:26 +00:00
Robert Noland
363fec5d16 Don't deref dev->dev_private before checking that it exists. 
Found with:	Coverity Prevent(tm)
CID:		2940

MFC after:	3 days
 2009-03-20 17:48:36 +00:00
Robert Noland
c20a7fc9f6 Only issue the wakeup and store the counter if vblank is enabled on 
the pipe.

MFC after:	3 days
 2009-03-20 04:53:12 +00:00
Robert Noland
c2dd8f68b0 Add a couple of radeon pci ids. 
MFC after:	3 days
 2009-03-20 04:49:48 +00:00
Robert Noland
9f85b82ccc Adjust the flags to bus_dmamem around here too. 
MFC after:	3 days
 2009-03-20 04:48:27 +00:00
Robert Noland
470fac3a17 Add some debugging so I can see when syscalls are being restarted 
consistantly.  After a lengthy irc discussion it seems like we
shouldn't need to worry about them, but it's nice to know about.

MFC after:	3 days
 2009-03-19 08:36:08 +00:00
Robert Noland
ea196ecaaa Rework vblank handling to try to resolve some reports of "slow" windows 
after vt switch or suspend.  I can't really test this on Intel right now
but I think I've heard reports of it on radeon as well.  I can't break
it on the radeon here.

MFC after:	3 days
 2009-03-19 08:34:04 +00:00
Robert Noland
324a23e9a2 Sync up the rest of the code that we use with what Intel is shipping 
-Some irq/vblank related changes that hopefully will help.
	-A little more cleanup while I'm here.

MFC after:	3 days
 2009-03-19 08:28:36 +00:00
Robert Noland
5a6ba2ffbc Pull in some suspend / resume changes from Intel's code 
Tested by:	mav@
MFC after:	3 days
 2009-03-19 08:22:56 +00:00
Robert Noland
b38c31bf40 Cast to (unsigned long) to make printf happy on i386 
MFC after:	3 days
 2009-03-17 05:10:12 +00:00
Robert Noland
c921ffc089 Add support for matching solely on vendor id. 
We will use this method with nouveau

MFC after:	3 days
 2009-03-17 03:53:44 +00:00
Robert Noland
f29130e3c2 Improve the debugging output of drm_mmap 
MFC after:	3 days
 2009-03-17 03:50:35 +00:00
Robert Noland
41a7f04fda Add list_for_each_prev to our linux compatibility. 
We need this for nouveau

MFC after:	3 days
 2009-03-17 03:49:24 +00:00
Robert Noland
a4501e547e Minor code cleanup 
MFC after:	3 days
 2009-03-17 03:46:37 +00:00
Robert Noland
d87f6722c5 We can have more than 3 pci resources 
MFC after:	3 days
 2009-03-17 03:44:36 +00:00
Robert Noland
ce3aaf8d2d Cast register maps and offsets to vm_offset_t 
MFC after:	3 days
 2009-03-17 03:39:09 +00:00
Robert Noland
b2a9095767 Change the logic around to match ati_pcigart. 
MFC after:	3 days
 2009-03-17 03:36:24 +00:00
Robert Noland
162e0ab8c1 Use flsl() here rather than ffsl() 
I discovered that we were computing page_order differently than linux.

MFC after:	3 days
 2009-03-17 03:32:12 +00:00