7 Commits

Author SHA1 Message Date
Ian Lepore
334b9c79c3 Add a public routine to set the L2 cache ram latencies. This can be
called by platform init routines to fine-tune cache performance.
2014-05-06 14:19:54 +00:00
Ian Lepore
7b41388248 Add defines for the bits in the PL310 debug control register.
This should have been part of r265444.
2014-05-06 14:08:42 +00:00
Ian Lepore
88b3694bd9 Move duplicated code to print l2 cache config into the common code. 2014-04-27 23:47:38 +00:00
Andrew Turner
a4244dbff9 Only work around errata when we are on a part where the erratum applies.
Reviewed by:	gonzo
2013-01-06 00:42:09 +00:00
Andrew Turner
5c9e101707 Document the known values of the RTL release field in the cache is register 2013-01-01 03:48:39 +00:00
Oleksandr Tymoshenko
7c5338d71e PL310 driver update:
- Add pl310.disable tunable to disable L2 cache altogether. In
    order to make sure that it's 100% disabled we use cache event
    counters for cache line eviction and read allocate events
    and panic if any of these counters increased. This is purely
    for debugging purpose
- Direct access DEBUG_CTRL and CTRL might be unavailable in
    unsecure mode, so use platform-specific functions for
    these registers
- Replace #if 1 with proper erratum numbers
- Add erratum 753970 workaround
- Remove wait function for atomic operations
- Protect cache operations with spin mutex in order to prevent race condition
- Disable instruction cache prefetch and make sure data cache
    prefetch is enabled in OMAP4-specific intialization
2012-12-31 21:19:44 +00:00
Oleksandr Tymoshenko
cf1a573f04 Merging projects/armv6, part 1
Cummulative patch of changes that are not vendor-specific:
	- ARMv6 and ARMv7 architecture support
	- ARM SMP support
	- VFP/Neon support
	- ARM Generic Interrupt Controller driver
	- Simplification of startup code for all platforms
2012-08-15 03:03:03 +00:00