Been in production for 3 years now. Gives Instant Frame relay to if_sr
and if_ar drivers, and PPPOE support soon. See:
ftp://ftp.whistle.com/pub/archie/netgraph/index.html
for on-line manual pages.
Reviewed by: Doug Rabson (dfr@freebsd.org)
Obtained from: Whistle CVS tree
In order to make this work, I created a pseudo-PHY driver to deal with
Macronix chips that use the built-in NWAY support and symbol mode port.
This is actually all of them, with the exception of the original MX98713
which presents its NWAY support via the MII serial interface.
The mxphy driver actually manipulates the controller registers directly
rather than using the miibus_readreg()/miibus_writereg() bus interface
since there are no MII registers to read. The mx driver itself pretends
that the NWAY interface is a PHY locayed at MII address 31 for the sole
purpose of allowing the mxphy_probe() routine to know when it needs to
attach to a host controller.
the AMI PCI controllers using the 8LD firmware interface (40LD firmware
will be supported as soon as I have hardware to test with).
These controllers are rebadged by Dell as the PERC, as well as by HP
and possibly other vendors.
apm_saver uses the apm_display() routine from the apm system to
"suspend" the "display" part of the machine.
This is beneficial for some laptops (or other machines with
non-traditional displays) that choke on the 'green' saver's
effect.
Another way of looking at this is that it's the same as a screen
saver that does an 'apm -d 0' to blank the display and an 'apm -d 1'
to bring it back. One probably ought to use these commands to make
sure the effect will be correct before using it unattended.
for the AN985 "Centaur" chip, which is apparently the next genetation
of the "Comet." The AN985 is also a tulip clone and is similar to the
AL981 except that it uses a 99C66 EEPROM and a serial MII interface
(instead of direct access to the PHY registers).
Also updated various documentation to mention the AN985 and created
a loadable module.
I don't think there are any cards that use this chip on the market yet:
the datasheet I got from ADMtek has boxes with big X's in them where the
diagrams should be, and the sample boards I got have chips without any
artwork on them.
2) s/MODLOAD/KMODLOAD/ to be consistent with the rest of the variables
(KMOD, KMODOWN, KMODGRP, etc) and definition of MODLOAD/UNLOAD in the
Makefile of the ATAPI module
3) textual fixups
the Davicom DM9100 and DM9102 chipsets, including the Jaton Corporation
XPressNet. Datasheet is available from www.davicom8.com.
The DM910x chips are still more tulip clones. The API is reproduced
pretty faithfully, unfortunately the performance is pretty bad. The
transmitter seems to have a lot of problems DMAing multi-fragment
packets. The only way to make it work reliably is to coalesce transmitted
packets into a single contiguous buffer. The Linux driver (written by
Davicom) actually does something similar to this. I can't recomment this
NIC as anything more than a "connectivity solution."
This driver uses newbus and miibus and is supported on both i386
and alpha platforms.
this PHY and the Davicom DM9101 have exactly the same register definitions.
One of them is probably a clone of the other. I'm not sure which.
This is needed for the Davicom DM9102 10/100 PCI ethernet driver which
will be committed shortly.
SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the
SiS chips can be found at www.sis.com.tw.
This is a fairly simple chipset. The receiver uses a 128-bit multicast
hash table and single perfect entry for the station address. Transmit and
receive DMA and FIFO thresholds are easily tuneable. Documentation is
pretty decent and performance is not bad, even on my crufty 486. This
driver uses newbus and miibus and is supported on both the i386 and
alpha architectures.
