6 Commits

Author SHA1 Message Date
Olivier Houchard
a43268a746 To prevent various race conditions in the RAS code, store and restore the
values in ARM_RAS_START and ARM_RAS_END at context switch time.

MFC after:	1 week
2009-02-12 23:23:30 +00:00
Rafal Jaworowski
e081d0ac19 Improve ARM_TP_ADDRESS and RAS area.
De-hardcode usage of ARM_TP_ADDRESS and RAS local storage, and move this
special purpose page to a more convenient place i.e. after the vectors high
page, more towards the end of address space. Previous location (0xe000_0000)
caused grief if KVA was to go beyond the default limit.

Note that ARM world rebuilding is required after this change since the
location of ARM_TP_ADDRESS is shared between kernel and userland.

Submitted by:	Grzegorz Bernacki (gjb AT semihalf dot com)
Reviewed by:	imp
Approved by:	cognet (mentor)
2008-02-05 10:22:33 +00:00
Olivier Houchard
f4c01f1508 Instead of using sysarch() to store-retrieve the tp, add a magic address,
ARM_TP_ADDRESS, where the tp will be stored. On CPUs that support it, a cache
line will be allocated and locked for this address, so that it will never go
to RAM. On CPUs that does not, a page is allocated for it (it will be a bit
slower, and is wrong for SMP, but should be fine for UP).
The tp is still stored in the mdthread struct, and at each context switch,
ARM_TP_ADDRESS gets updated.

Suggested by:   davidxu
2005-02-26 18:59:01 +00:00
Olivier Houchard
a74985cdd4 Implement two new sysarch for arm, ARM_GET_TP and ARM_SET_TP, to work around
the lack of tls on arm.
2005-02-25 22:56:16 +00:00
Warner Losh
d8315c79d9 Start all license statements with /*- 2005-01-05 21:58:49 +00:00
Olivier Houchard
371853e562 Add MD syscalls to sync the icache and to drain the write buffer.
Obtained from:	NetBSD
2004-09-23 21:56:01 +00:00