of the ABI of the currently executing image. Change some places to test
the flags instead of explicit comparing with address of known sysentvec
structures to determine ABI features.
Discussed with: dchagin, imp, jhb, peter
and ifnet functions
- add memory barriers to <machine/atomic.h>
- update drivers to only conditionally define their own
- add lockless producer / consumer ring buffer
- remove ring buffer implementation from cxgb and update its callers
- add if_transmit(struct ifnet *ifp, struct mbuf *m) to ifnet to
allow drivers to efficiently manage multiple hardware queues
(i.e. not serialize all packets through one ifq)
- expose if_qflush to allow drivers to flush any driver managed queues
This work was supported by Bitgravity Inc. and Chelsio Inc.
sdhci supports up to 65535 blocks transfers, at91_mci - one block.
Enable multiblock operations disabled before to follow at91_mci driver
limitations.
Reviewed by: imp@
machine arm
device mem
options GEOM_BSD
options GEOM_MBR
Remove the first two from all kernel configuration files and
change geom_bsd and geom_mbr from standard to optional.
This uses the common U-Boot support lib (sys/boot/uboot, already used on
FreeBSD/powerpc), and assumes the underlying firmware has the modern API for
stand-alone apps enabled in the config (CONFIG_API).
Only netbooting is supported at the moment.
Obtained from: Marvell, Semihalf
FreeBSD 8-CURRENT was tested and run successfully on the following eval
boards and devices :
* DB-88F5182, DB-88F5281 (Orion based)
* DB-88F6281, RD-88F6281 (Kirkwood based)
* DB-78100 (Discovery based)
For more detailed info on build instructions and other examples please refer
to http://wiki.freebsd.org/FreeBSDMarvell
Obtained from: Marvell, Semihalf
* Orion
- 88F5181
- 88F5182
- 88F5281
* Kirkwood
- 88F6281
* Discovery
- MV78100
The above families of SOCs are built around CPU cores compliant with ARMv5TE
instruction set architecture definition. They share a number of integrated
peripherals. This commit brings support for the following basic elements:
* GPIO
* Interrupt controller
* L1, L2 cache
* Timers, watchdog, RTC
* TWSI (I2C)
* UART
Other peripherals drivers will be introduced separately.
Reviewed by: imp, marcel, stass (Thanks guys!)
Obtained from: Marvell, Semihalf
The physical page which we clear is accessed via additional temp kernel
mapping for the period of zeroing operation. However in systems with virtual
d-cache (most ARMs) when write-allocate feature is enabled, we can have
modified but unflushed content pertaining to this physical page still in the
d-cache due to its primary (pre-existing) mapping. In such scenario that
cached content upon flush is likely to overwrite [portions of] the physical
page we want to zero here..
This is a general problem with multiple virtual mappings covering the same
physical page with write-allocate and virtual d-cache: there is inherent
potential for corruptions of this kind, which are not easily resolved; it is
best policy that such multiple mappings be not allowed.
Obtained from: Marvell, Semihalf
After I removed all the unit2minor()/minor2unit() calls from the kernel
yesterday, I realised calling minor() everywhere is quite confusing.
Character devices now only have the ability to store a unit number, not
a minor number. Remove the confusion by using dev2unit() everywhere.
This commit could also be considered as a bug fix. A lot of drivers call
minor(), while they should actually be calling dev2unit(). In -CURRENT
this isn't a problem, but it turns out we never had any problem reports
related to that issue in the past. I suspect not many people connect
more than 256 pieces of the same hardware.
Reviewed by: kib
to the C99 style. At least, it is easier to read sysent definitions
that way, and search for the actual instances of sigcode etc.
Explicitely initialize sysentvec.sv_maxssiz that was missed in most
sysvecs.
No objection from: jhb
MFC after: 1 month
- Fix nexus_setup_intr() abuse of setting up multiple IRQs in one go. Calling
arm_setup_irqhandler() in loop is bogus, as there's just one cookie given
from the caller and it is overwritten in each iteration so that only the
last handler's cookie value prevails.
- Proper intr masking/unmasking handling: the IRQ source is masked at PIC level
only after the last handler has been removed from the list.
Reviewed by: cognet, imp, sam, stass
Obtained from: Grzegorz Bernacki gjb ! semihalf dot com
don't inline the locking primitives, and only grab those parts of mii
that we really need. Other space optimizations are too agressive for
the generic file (removing all of usb, and loading it as kernel
modules).
o It has been tested only on KB9202, KB9202A and KB9202B boards
o Better comments about hints
o option<space><tab>
o Add newer SX_NOINLINE option.
o Fix a few comments
driver will need more serious help to work with an interrupt driven
path. There's many subtleties in driving the DMA engine with
interrupts in many configurations. Best to not "guess" what the right
way would be and mislead people.
memory allocation. It was change to include the range in the normal
memory area, so these ifdef'd out special cases are no longer useful
to keep around.
first one. U-boot, for example, uses the second register to store
MAC.[1]
- Use random MAC address if none configured instead of failing.
Submitted by: Bjorn Konig <bkoenig@alpha-tierchen.de> [1]
Reviewed by: imp
Approved by: kib (mentor)
MFC after: 1 week
