Commit Graph

551 Commits

Author SHA1 Message Date
Josh Paetzel
c77037f16f Fix indentation for r323068
PR:	220170
Reported by:	lidl
MFC after:	3 days
Pointyhat to:	jpaetzel
2017-09-19 20:40:05 +00:00
Andrew Turner
ca289945b2 Add the ARMv8.3 ID register fields. These were found in the A-Profile
exploration tools documentation:
https://developer.arm.com/products/architecture/a-profile/exploration-tools

Sponsored by:	DARPA, AFRL
2017-09-15 12:57:34 +00:00
Andrew Turner
bcf2b954c3 Add support for handling undefined instructions in userspace and the
kernel. We can register callbacks to perform the required operation on the
saved registers before returning.

This is initially used to work around a bug in old versions of QEMU that
trigger such an exception when reading from an ID register when it should
load z zero value.

I expect this could be used with other exception types, e.g. to emulate
special register access from userland.

Sponsored by:	DARPA, AFRL
2017-09-14 17:29:51 +00:00
John Baldwin
c2f37b9245 Add AT_HWCAP and AT_EHDRFLAGS on all platforms.
A new 'u_long *sv_hwcap' field is added to 'struct sysentvec'.  A
process ABI can set this field to point to a value holding a mask of
architecture-specific CPU feature flags.  If an ABI does not wish to
supply AT_HWCAP to processes the field can be left as NULL.

The support code for AT_EHDRFLAGS was already present on all systems,
just the #define was not present.  This is a step towards unifying the
AT_* constants across platforms.

Reviewed by:	kib
MFC after:	1 month
Differential Revision:	https://reviews.freebsd.org/D12290
2017-09-14 14:26:55 +00:00
Ilya Bakulin
61df30cfd4 Add MMCCAM-enabled kernel config for arm64
Approved by:	imp (mentor)
Differential Revision:	https://reviews.freebsd.org/D12114
2017-09-11 19:07:42 +00:00
Marcin Wojtas
885a74181c Expand Marvell NIC description in arm64 GENERIC config
Suggested by: emaste
2017-09-11 19:00:53 +00:00
Marcin Wojtas
7ca8a2b385 Enable compilation of Marvell NETA controller with arm64 GENERIC
This patch enables network operation on Marvell Armada 3700 SoC.

Submitted by: Patryk Duda <pdk@semihalf.com>
Obtained from: Semihalf
Sponsored by: Semihalf
Differential Revision: https://reviews.freebsd.org/D12259
2017-09-09 11:56:48 +00:00
Marcin Wojtas
e49e3ec31e Add support for uart_mvebu driver arm64 GENERIC config
This patch enables console output on Armada 3700 SoCs
with kernel GENERIC.

Submitted by: Patryk Duda <pdk@semihalf.com>
Obtained from: Semihalf
Sponsored by: Semihalf
Differential Revision: https://reviews.freebsd.org/D12251
2017-09-09 11:46:34 +00:00
Marcin Wojtas
840d633f12 Enable compilation of Marvell EHCI driver in arm64 GENERIC
Enabled driver can be used on boards equipped with Marvell Armada 3700 SoC.

Submitted by: Patryk Duda <pdk@semihalf.com>
Obtained from: Semihalf
Sponsored by: Semihalf
Differential Revision: https://reviews.freebsd.org/D12256
2017-09-09 11:16:10 +00:00
Marcin Wojtas
705f4b2ceb Enable compilation of Marvell XHCI driver in arm64 GENERIC
Enabled driver can be used on boards equipped with Marvell Armada
3700/7k/8k SoCs.

Submitted by: Patryk Duda <pdk@semihalf.com>
Obtained from: Semihalf
Sponsored by: Semihalf
Differential Revision: https://reviews.freebsd.org/D12253
2017-09-09 10:58:45 +00:00
Andrew Turner
c1649fdb02 Not all CPUs handle reading ID_AA64MMFR2_EL1 (e.g. qemu), disable it for now.
Sponsored by:	DARPA, AFRL
2017-09-08 08:02:06 +00:00
Andrew Turner
f9fc9faa3a Fix the SVE ID field shift.
Sponsored by:	DARPA, AFRL
2017-09-07 19:52:04 +00:00
Andrew Turner
130be885e6 Add the ATS1E1 case to the ID_AA64MMFR1_EL1 decoding.
Sponsored by:	DARPA, AFRL
2017-09-07 19:51:17 +00:00
Andrew Turner
d28b950a4d Use the correct mask when printing undecoded fields from the
ID_AA64MMFR2_EL1 register.

Sponsored by:	DARPA, AFRL
2017-09-07 18:58:55 +00:00
Andrew Turner
d1c2e46d9c Fix a mismerge, make sure PRINT_ID_AA64_MMFR2 has a unique value.
Sponsored by:	DARPA, AFRL
2017-09-07 16:43:12 +00:00
Andrew Turner
1a2e5c004d Fix the value of ID_AA64ISAR1_DPB_SHIFT, the field is bits 3:0.
Sponsored by:	DARPA, AFRL
2017-09-07 16:12:56 +00:00
Andrew Turner
f45dc6945b Add the ARMv8.2 ID register additions and use them to decode the register
values. As not all assemblers understand the new ID_AA64MMFR2_EL1 register
add a macro to access it. This seems to be safe for older CPUs to read this
new register, with them returning zero.

Sponsored by:	DARPA, AFRL
2017-09-07 15:45:56 +00:00
Andrew Turner
0f962c6deb Uppercase the special register names in identcpu to be more consistent with
the other source files.

Sponsored by:	DARPA, AFRL
2017-09-07 15:30:13 +00:00
Andrew Turner
a0f16159bd Make the bit mask of ARMv8 ID registers to print sparse to keep values
close, but without having to change all values when new registers are added.

Sponsored by:	DARPA, AFRL
2017-09-07 15:24:47 +00:00
Andrew Turner
5ad42f79fb Add more ARM Ltd parts to the list of knows CPUs.
Submitted by:	Jon Brawn <jon@brawn.org>
2017-09-07 15:02:57 +00:00
Marcin Wojtas
eedd5eafbe Add Marvell RTC driver to arm64 GENERIC config
Marvell Armada 80x0/70x0 SoC family uses same RTC IP as
Armada 38x. This patch adds necessary files and enable driver in
GENERIC config.

Submitted by: Rafal Kozik <rk@semihalf.com>
Obtained from: Semihalf
Sponsored by: Semihalf
Differential Revision: https://reviews.freebsd.org/D12200
2017-09-05 05:50:01 +00:00
Marcin Wojtas
d7d8ab0316 Add ARM Cortex A72 to CPU list
This change is required to properly detect CPUs
on Marvell Armada 80x0/70x0 SoC family.

Submitted by: Rafal Kozik <rk@semihalf.com>
Reviewed by: andrew, cognet (mentor)
Approved by: cognet (mentor)
Sponsored by: Semihalf
Differential Revision: https://reviews.freebsd.org/D12184
2017-09-03 08:32:33 +00:00
Josh Paetzel
9d0ec2a920 Revert r323087
This needs more thinking out and consensus, and the commit message
was wrong AND there was a typo in the commit.

pointyhat:	jpaetzel
2017-09-01 17:03:48 +00:00
Josh Paetzel
0be04b100c Take options IPSEC out of GENERIC
PR:	220170
Submitted by:	delphij
Reviewed by:	ae, glebius
MFC after:	2 weeks
Differential Revision:	D11806
2017-09-01 15:54:53 +00:00
Andrew Turner
5ea26aec6e Add support for quirks while enabling secondary CPUs. This uses the fdt
compatible string to check if the board is compatible with a given quirk.
It's possible this will be moved later, however as it's currently only used
by the MP code put it there.

So far the only instance of a quirk is when the list of CPUs may be
incorrect. This can happen on virtual machines with a hard coded
devicetree, but where the user may then set the number of CPUs as an
argument. This is the case on the ARM models so include the model specific
compat strings for these, including the spelling mistake found in some of
the OpenplatformPkg dtb files.

Sponsored by:	DARPA, AFRL
2017-08-31 20:48:05 +00:00
Josh Paetzel
3b65550eec Allow kldload tcpmd5
PR:	220170
MFC after:	2 weeks
2017-08-31 20:16:28 +00:00
Andrew Turner
dab076c004 Remove an unneeded call to pmap_invalidate_all. This was never called as
the anyvalid variable is never set.

MFC after:	1 week
Sponsored by:	DARPA, AFRL
2017-08-22 18:20:25 +00:00
Andrew Turner
012faa32f9 Fix a bug in pmap_protect where we invalidate the wrong page. With this we
can now remove an unneeded call to invalidate all entries.

MFC after:	1 week
Sponsored by:	DARPA, AFRL
2017-08-22 17:38:06 +00:00
Andrew Turner
e8e65e28ca Fix a comment on uncommitted work. 2017-08-22 13:53:53 +00:00
Andrew Turner
6683b30c03 Move the l0 pagetable address to struct mdproc. It is a property of the
whole process so should live there.

Sponsored by:	DARPA, AFRL
2017-08-22 13:16:14 +00:00
Andrew Turner
cbf2160e81 Improve the performance of the arm64 thread switching code.
The full system memory barrier around a TLB invalidation is stricter than
required. It needs to wait on accesses to main memory, with just the weaker
store variant before the invalidate. As such use the dsb istst, tlbi, dlb
ish sequence already used in pmap.

The tlbi instruction in this sequence is also unnecessarily using a
broadcast invalidate when it just needs to invalidate the local CPUs TLB.
Switch to a non-broadcast variant of this instruction.

Sponsored by:	DARPA, AFRL
2017-08-21 18:12:32 +00:00
Mark Johnston
01938d3666 Rename mkdumpheader() and group EKCD functions in kern_shutdown.c.
This helps simplify the code in kern_shutdown.c and reduces the number
of globally visible functions.

No functional change intended.

Reviewed by:	cem, def
Sponsored by:	Dell EMC Isilon
Differential Revision:	https://reviews.freebsd.org/D11603
2017-08-18 04:04:09 +00:00
Mark Johnston
50ef60dabe Factor out duplicated kernel dump code into dump_{start,finish}().
dump_start() and dump_finish() are responsible for writing kernel dump
headers, optionally writing the key when encryption is enabled, and
initializing the initial offset into the dump device.

Also remove the unused dump_pad(), and make some functions static now that
they're only called from kern_shutdown.c.

No functional change intended.

Reviewed by:	cem, def
Sponsored by:	Dell EMC Isilon
Differential Revision:	https://reviews.freebsd.org/D11584
2017-08-18 03:52:35 +00:00
Ed Maste
e7b993842e arm64: return error instead of panic in unimplemented ptrace ops
We don't need a panic as a reminder that these need to be implemented.

Reported by:	Shawn Webb
MFC after:	3 week
Sponsored by:	The FreeBSD Foundation
2017-08-17 19:16:23 +00:00
Andrew Turner
062c276886 Add support for multiple GICv3 ITS devices. For this we add sc_irq_base
and sc_irq_length to the softc to handle the base number of IRQs available,
make gicv3_get_nirqs return the number of available interrupt IDs, and
limit which CPUs we send interrupts to based on the numa domain.

The last point is only strictly needed on a dual socket ThunderX where we
are unable to send MSI/MSI-X interrupts between sockets.

Sponsored by:	DARPA, AFRL
2017-08-13 18:54:51 +00:00
John Baldwin
992029ba10 Reliably enable debug exceptions on all CPUs.
Previously, debug exceptions were only enabled on the boot CPU if
DDB was enabled in the dbg_monitor_init() function.  APs also called
this function, but since mp_machdep.c doesn't include opt_ddb.h, the
APs ended up calling an empty stub defined in <machine/debug_monitor.h>
instead of the real function.  Also, if DDB was not enabled in the kernel,
the boot CPU would not enable debug exceptions.

Fix this by adding a new dbg_init() function that always clears the OS
lock to enable debug exceptions which the boot CPU and the APs call.
This function also calls dbg_monitor_init() to enable hardware breakpoints
from DDB on all CPUs if DDB is enabled.  Eventually base support for
hardware breakpoints/watchpoints will need to move out of the DDB-only
debug_monitor.c for use by userland debuggers.

Reviewed by:	andrew
Differential Revision:	https://reviews.freebsd.org/D12001
2017-08-12 18:42:54 +00:00
John Baldwin
c9ee3caf19 Don't panic for PT_GETFPREGS.
Only fetch the VFP state from the CPU if the thread whose registers are
being requested is the current thread.  If a stopped thread's registers
are being fetched by a debugger, the saved state in the PCB is already
valid.

Reviewed by:	andrew
MFC after:	1 week
2017-08-12 18:38:18 +00:00
John Baldwin
319e8f3e36 Fix a typo. 2017-08-11 22:47:32 +00:00
Andrew Turner
1f15260790 Mark each cpu in the appropriate cpuset_domain set. This allows devices to
handle cases where they can only run on a single domain.

To allow all devices access to this set we need to move reading the domain
earlier in the boot as it was previously handled in the CPU driver, however
this is too late for the GICv3 ITS driver.

Sponsored by:	DARPA, AFRL
2017-08-05 20:57:34 +00:00
Andrew Turner
49f347f450 Start to teach the GICv3 driver about NUMA. On ThunderX we may have
multiple ITS devices, however we only want a single ITS device to be
configured on each CPU. To fix this only enable ITS when the node matches
the CPUs node.

Sponsored by:	DARPA, AFRL
2017-08-04 13:08:45 +00:00
Andrew Turner
dbba8930ce Read the numa-node-id property from each CPU node. This will initially be
used to support the dual package ThunderX where we need to send MSI/MSI-X
interrupts to the same package as the device the interrupt came from.

Sponsored by:	DARPA, AFRL
2017-08-04 10:33:22 +00:00
Emmanuel Vadot
48ee531892 arm64: Add Allwinner H5 SoC
Allwinner H5 is an H3 (arm32) with Cortex A53 cores.
Add support for it and enable it in GENERIC kernel config

Tested on: OrangePi PC2
2017-08-02 20:19:19 +00:00
Andrew Turner
ce793a529b Pass the last exception trap frame to kdb_trap. This allows show registers
in ddb to show the traps registers, and not the registers from within the
panic call.

Sponsored by:	DARPA, AFRL
2017-07-26 17:39:10 +00:00
Andrew Turner
a2d16bc541 Add support for passing FPU_KERN_NOCTX to fpu_kern_enter on arm64. This
will be used to call into UEFI from the kernel.

Sponsored by:	DARPA, AFRL
2017-07-18 16:36:32 +00:00
Emmanuel Vadot
0166fb5d59 arm64: Add Allwinner I2C controller to GENERIC kernel 2017-07-09 12:53:02 +00:00
Andrew Turner
db7b284bd6 In the arm64 pmap_remove, when removing a full superpage there is no need
to demote it to 512 pages, then remove each of these. We can just remove
the l2 map directly. This is what the intel pmaps already do.

Sponsored by:	DARPA, AFRL
2017-07-02 08:52:08 +00:00
Andrew Turner
567dec3d2b Remove all calls to cpu_dcache_wb_range from the arm64 pmap code. These
were unneeded as we tell the tlb the pagetables are in cached memory. This
gives us a small, but statistically significant improvement over just
removing the PTE_SYNC cases.

While here remove PTE_SYNC, it's now unneeded.

Sponsored by:	DARPA, AFRL
2017-07-01 09:38:52 +00:00
Jason A. Harmening
eb36b1d0bc Clean up MD pollution of bus_dma.h:
--Remove special-case handling of sparc64 bus_dmamap* functions.
  Replace with a more generic mechanism that allows MD busdma
  implementations to generate inline mapping functions by
  defining WANT_INLINE_DMAMAP in <machine/bus_dma.h>.  This
  is currently useful for sparc64, x86, and arm64, which all
  implement non-load dmamap operations as simple wrappers
  around map objects which may be bus- or device-specific.

--Remove NULL-checked bus_dmamap macros.  Implement the
  equivalent NULL checks in the inlined x86 implementation.
  For non-x86 platforms, these checks are a minor pessimization
  as those platforms do not currently allow NULL maps.  NULL
  maps were originally allowed on arm64, which appears to have
  been the motivation behind adding arm[64]-specific barriers
  to bus_dma.h, but that support was removed in r299463.

--Simplify the internal interface used by the bus_dmamap_load*
  variants and move it to bus_dma_internal.h

--Fix some drivers that directly include sys/bus_dma.h
  despite the recommendations of bus_dma(9)

Reviewed by:	kib (previous revision), marius
Differential Revision:	https://reviews.freebsd.org/D10729
2017-07-01 05:35:29 +00:00
Andrew Turner
2da3e34e0a Remove a blank line accidentally added in r320403. 2017-06-30 14:45:43 +00:00
Andrew Turner
355ffcc842 Add parentheses missed in r320388
Sponsored by:	DARPA, AFRL
2017-06-27 16:30:01 +00:00