Commit Graph

109 Commits

Author SHA1 Message Date
Wojciech Macek
9d6cd3d858 Introduce support for Annapurna Alpine CCU and NB devices
This commit adds drivers for Alpine Cache Coherency Unit
and North Bridge Service whose task is to configure
the system fabric and enable cache coherency.

Obtained from:         Semihalf
Submitted by:          Michal Stanek <mst@semihalf.com>
Sponsored by:          Annapurna Labs
Reviewed by:           wma
Differential Revision: https://reviews.freebsd.org/D7565
2016-09-07 05:34:41 +00:00
Jared McNeill
fa1cbf00d7 Add generic device-tree cpufreq driver. 2016-09-06 21:36:20 +00:00
Andrew Turner
727c18a84f Split out the FDT parts of the GICv2 interrupt controller driver. This will
allow us to add an ACPI attachment for arm64.

Obtained from:	ABT Systems Ltd
MFC after:	1 month
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D7307
2016-08-01 16:29:04 +00:00
Andrew Turner
3fc155dc64 Introduce MSI and MSI-X support to intrng. This adds a new msi device
interface with 5 methods to mirror the 5 MSI/MSI-X methods in the pcib
interface. The pcib driver will need to perform a device specific lookup
to find the MSI controller and pass this to intrng as the xref. Intrng
will finally find the controller and have it handle the requested operation.

Obtained from:	ABT Systems Ltd
MFH:		yes
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D5985
2016-05-16 09:11:40 +00:00
Ruslan Bukin
30b72b6871 Move arm's devmap to some generic place, so it can be used
by other architectures.

Reviewed by:	imp
Differential Revision:	https://reviews.freebsd.org/D6091
Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-04-26 11:53:37 +00:00
Andrew Turner
59c3cb81c1 Rename ARM_INTRNG and MIPS_INTRNG to INTRNG. This will help with machine
independent code that needs to know about INTRNG such as PCI drivers.

Obtained from:	ABT Systems Ltd
Sponsored by:	The FreeBSD Foundation
2016-04-15 16:05:41 +00:00
Andrew Turner
820d50e549 Sort so pic_if.m is in the correct location with the other kern files.
Obtained from:	ABT Systems Ltd
Sponsored by:	The FreeBSD Foundation
2016-04-14 15:52:11 +00:00
Zbigniew Bodek
c43a86743c Reduce OFW PCI code duplication - involves ARM, PPC and SPARC64
Import portions of the PowerPC OF PCI implementation into new file
"ofwpci.c", common for other platforms. The files ofw_pci.c and ofw_pci.h
from sys/powerpc/ofw no longer exist. All required declarations are moved
to sys/dev/ofw/ofwpci.h. This creates a new ofw_pci_write_ivar() function
and modifies some others methods. Most functions contain existing ppc
implementations in the majority unchanged. Now there is no need to have
multiple identical copies of methods for various architectures.

Requested by:  jhibbits
Reviewed by:   jhibbits, marius
Submitted by:  Marcin Mazurek <mma@semihalf.com>
Obtained from: Semihalf
Sponsored by:  Annapurna Labs
Differential Revision: https://reviews.freebsd.org/D4879
2016-03-29 15:19:56 +00:00
Bjoern A. Zeeb
9e9a7326dd Adding pci_host_generic unconditionally breaks ARM boards with a PCI(e) interface.
Make it a device option to be included in the kernel configs that request this file.

Reported by:	mmel
Suggested by:	mmel
Reviewed by:	mmel
Differential Revision:	https://reviews.freebsd.org/D5699
2016-03-22 12:12:01 +00:00
Bjoern A. Zeeb
667060fe6c Allow pci_host_generic to be compiled into ARM kernels, used, e.g., in
simulators.

Sponsored by:	DARPA/AFRL
2016-03-18 23:55:25 +00:00
Andrew Turner
8d88b09320 Build ofw_cpu.c on all ARM configs using FDT. As we mve towards using the
Linux dts files these are more likely to have cpu nodes we can attach to.

Sponsored by:	ABT Systems Ltd
2016-02-28 09:35:37 +00:00
Svatopluk Kraus
c4a4eb59e3 Rename busdma_machdep.c to busdma_machdep-v4.c, pmap.c to pmap-v4.c
and trap.c to trap-v4.c to be plain and consistent with other armv4
specific files.
2016-02-20 07:45:21 +00:00
Andrew Turner
632381ed9d Move the twsi driver source to be under iicbus. It is in a separate
directory as it is expected multiple attachments will be added for the SoC
families that use this hardware.

Sponsored by:	ABT Systems Ltd
2016-02-14 23:51:13 +00:00
Michal Meloun
afdcfee483 ARM: Remove support for xscale i80219 and i80321 CPUs. We haven't single
supported config/board with these CPUs.
2016-02-03 09:15:44 +00:00
Michal Meloun
e3f95afdec ARM: All remaining functions in cpufunc_asm_arm10.S are identical with
functions in cpufunc_asm_arm9.S. Use arm9 variants and remove
cpufunc_asm_arm10.S completly.
2016-02-02 14:53:34 +00:00
Michal Meloun
46c901268a ARM: Split swtch.S into common, ARMv4 and ARMv6 parts. Cleanup them. 2016-01-30 08:02:12 +00:00
Michal Meloun
4f7da057cb ARM: After removal of old pmap-v6 code, rename pmap-v6-new.c to pmap-v6.c. 2016-01-29 11:00:33 +00:00
Michal Meloun
41a7c569b0 ARM: remove old pmap-v6 code. The new pmap-v6 is mature enough, and
dual implementation is showstopper for major cleanup.

This patch only removes old code from tree. Cleanups will follow asap.
2016-01-29 10:31:54 +00:00
Zbigniew Bodek
595f8a5905 Introduce support for HW watchpoints and single stepping for ARMv6/v7
Allows for using hardware watchpoints for 1, 2, 4, 8 byte long addresses.
The default configuration of watchpoint is RW but code allows to select
RO or WO and X.
Since debugging registers are per-CPU (CP14) the watchpoint is set on
the CPU that was lucky (or not) to enter DDB.

HW breakpoints are used to perform single step in KDB.
When HW breakpoint is enabled all watchpoints are temporary disabled
to avoid recursive abort on both watchpoint and breakpoint.
In case of branch, the breakpoint is set to both - next instruction
and possible branch address. This requires at least 2 breakpoints
supported in the CPU however this is a must for ARMv6/v7 CPUs.

Reviewed by:   imp
Submitted by:  Zbigniew Bodek <zbb@semihalf.com>
Obtained from: Semihalf
Sponsored by:  Juniper Networks Inc.
Differential Revision: https://reviews.freebsd.org/D4037
2016-01-25 18:02:28 +00:00
Ian Lepore
bc7b930020 Implement OF_decode_addr() for arm. Move most of powerpc's implementation
into a new function that other platforms can share.

This creates a new ofw_reg_to_paddr() function (in a new ofw_subr.c file)
that contains most of the existing ppc implementation, mostly unchanged.
The ppc code now calls the new MI code from the MD code, then creates a
ppc-specific bus_space mapping from the results. The new arm implementation
does the same in an arm-specific way.

This also moves the declaration of OF_decode_addr() from ofw_machdep.h to
openfirm.h, except on sparc64 which uses a different function signature.

This will help all FDT platforms to set up early console access using
OF_decode_addr().
2015-12-21 18:07:32 +00:00
Adrian Chadd
2b3ad18853 [intrng] Migrate the intrng code from sys/arm/arm to sys/kern/subr_intr.c.
The ci20 port (by kan@) is going to reuse almost all of the intrng code
since the SoC in question looks suspiciously like someone took an ARM
SoC design and replaced the ARM core with a MIPS core.

* migrate out the code;
* rename ARM_ -> INTR_;
* rename arm_ -> intr_;
* move the interrupt flush routine from intr.c / intrng.c into
  arm/machdep_intr.c - removing the code duplication and removing
  the ARM specific bits from here.

Thanks to the Star Wars: The Force Awakens premiere line for allowing
me a couple hours of quiet time to finish the universe builds.

Tested:

* make universe

TODO:

* The structure definitions in subr_intr.c still includes machine/intr.h
  which requires one duplicates all of the intrng definitions in
  the platform code (which kan has done, and I think we don't have to.)

  Instead I should break out the generic things (function declarations,
  common intr structures, etc) into a separate header.

* Kan has requested I make the PIC based IPI stuff optional.
2015-12-18 05:43:59 +00:00
Konstantin Belousov
4d22d07a07 Add support for usermode (vdso-like) gettimeofday(2) and
clock_gettime(2) on ARMv7 and ARMv8 systems which have architectural
generic timer hardware. It is similar how the RDTSC timer is used in
userspace on x86.

Fix a permission problem where generic timer access from EL0 (or
userspace on v7) was not properly initialized on APs.

For ARMv7, mark the stack non-executable. The shared page is added for
all arms (including ARMv8 64bit), and the signal trampoline code is
moved to the page.

Reviewed by:	andrew
Discussed with:	emaste, mmel
Sponsored by:	The FreeBSD Foundation
Differential revision:	https://reviews.freebsd.org/D4209
2015-12-07 12:20:26 +00:00
Andrew Turner
dd76e27f7a Move hdmi_if.m to files.arm so other kernel configs can use it. 2015-11-21 16:25:03 +00:00
Andrew Turner
ed18006cbf Create device options for the two common ARM timers.
Sponsored by:	ABT Systems Ltd
2015-11-21 16:23:56 +00:00
Andrew Turner
210d6af74d Move more bus_space_* files to be built by files.arm. This leaves the
definition in a file.* file under sys/arm/arm in the few cases we need it
for non-fdt platforms.

Sponsored by:	ABT Systems Ltd
2015-11-21 15:30:08 +00:00
Conrad Meyer
3d3e385e75 Add libkern ffsll() for parity with flsll()
Sponsored by:	EMC / Isilon Storage Division
Differential Revision:	https://reviews.freebsd.org/D3962
2015-10-22 20:28:37 +00:00
Ian Lepore
686450c898 Import ARM_INTRNG, the "next generation" interrupt architecture for arm
and armv6 architecures.  The primary enhancement over the old design is
support for hierarchical interrupt controllers (such as a gpio driver
which can receive interrupts from a root PIC and act as a PIC itself for
clients interested in handling a change of gpio pin state as an
interrupt).  The new code also provides an infrastructure for mapping
interrupts described in metadata in the form of a "controller reference
plus interrupt number" tuple into the simple "0-n" flat numeric space
understood by rman and the bus resource mechanisms.

Use of the new code is enabled by setting the ARM_INTRNG option, and by
making a few simple changes to the platform's support code.  In addition
each existing PIC driver needs changes to be ready for INTRNG; this commit
contains the changes for the arm/gic driver, which most armv6 SoCs use, but
it does not enable the new code yet on any platform.

This project has been many years in the making, starting as a GSoC project
by Jakub Klama (jceel@) in 2012.  That didn't get committed right away and
the source base evolved out from under it to some degree.  In 2014 I rebased
the diffs to then -current and did some enhancements in the area of mapping
interrupt numbers and storing associated fdt data, then the project went
cold again for a while.  Eventually Svata Kraus took that work in progress
and did another big round of work on it, removing most of the remaining
rough edges.  Finally I took that and made one more pass through it, mostly
disabling the "INTR_SOLO" feature for now, pending further design
discussions on how to most efficiently dispatch a pending interrupt through
more than one layer of PIC.  The current code with the INTR_SOLO feature
disabled uses approximate 100 extra cpu cycles for each cascaded PIC the
interrupt has to be passed to, so what's left to do is about efficiency, not
correct operation.

Differential Revision:	https://reviews.freebsd.org/D2047
2015-10-18 18:26:19 +00:00
Bjoern A. Zeeb
07709c9b99 2nd try, after r289319:
HWPMC depends on pmu.c even if device pmu is not specified.
Would be great if we could just automatically enabled "device pmu"
if we try to compile in HWPMC.

Also several old kernel cnfigurations seem to have HWPMC enabled but are
pre-FDT and thus fail.  So make pmu.c depend on fdt in case of hwpmc as
well.

MFC after:		2 weeks
Sponsored by:		DARPA/AFRL
Differential Revision:	https://reviews.freebsd.org/D3877
2015-10-15 01:51:10 +00:00
Bjoern A. Zeeb
184b91e538 Revert r289319 as it seems some ARM kernels include HWPMC but no FDT.
To me that seems broken as certain interrupts will never be handled
properly.  I'll re-open D3877 and we can seek a better solution and
try again.  For now go back to that state and avoid compile time errors.
2015-10-14 18:53:34 +00:00
Bjoern A. Zeeb
48d1ff3a2d HWPMC depends on pmu.c even if device pmu is not specified.
Would be great if we could just automatically enabled "device pmu"
if we try to compile in HWPMC.

MFC after:		2 weeks
Sponsored by:		DARPA/AFRL
Reviewed by:		andrew
Differential Revision:	https://reviews.freebsd.org/D3877
2015-10-14 17:07:24 +00:00
Andrew Turner
b1bddf4039 Move pmu.c to files.arm and rename the option to pmu. This is not hwpmc
specific as we may use the pmu registers for other uses. No configs seem
to currently build this.

This will allow for more use of this device.

Discussed with:	bz
Sponsored by:	ABT Systems Ltd
2015-10-07 13:19:44 +00:00
Ed Maste
67da38c51c Move kbd.c to main sys/conf/files list
It is (optionally) used on all architectures.

Sponsored by:	The FreeBSD Foundation
2015-09-21 17:31:11 +00:00
Luiz Otavio O Souza
5df539274f Add alternate descriptors support for if_dwc.
This also adds a newbus interface that allows a SoC to override the
following settings:

 - if_dwc specific SoC initialization;
 - if_dwc descriptor type;
 - if_dwc MII clock.

This seems to be an old version of the hardware descriptors but it is
still in use in a few SoCs (namely Allwinner A20 and Amlogic at least).

Tested on Cubieboard2 and Banana pi.

Tested for regressions on Altera Cyclone by br@ (old version).

Obtained from:	NetBSD
2015-09-20 14:13:29 +00:00
Andrew Turner
6c50960be6 Add support for __aeabi_memclr4, clang 3.7 calls it.
Sponsored by:	ABT Systems Ltd
2015-07-09 20:54:38 +00:00
Ruslan Bukin
4f4d15f0d0 Allow DTrace to be compiled-in to the kernel.
This will require for AArch64 as we dont have modules yet.

Sponsored by:	HEIF5
Sponsored by:	ARM Ltd.
Differential Revision:	https://reviews.freebsd.org/D1997
2015-06-10 15:53:39 +00:00
Andrew Turner
e4ca149905 Add the gic to files.arm under "device gic" and use it with the
CUBIEBOARD2 config. This is common across a few SoCs so should be a common
option.
2015-05-10 09:33:03 +00:00
Andrew Turner
46b1fe9224 Add a driver for the ARM Power State Coordination Interface (PSCI). This
handles versions 0.1 and 0.2 of the standard on 32-bit ARM.

With this driver we can shutdown in QEMU. Further work is needed to
turn secondary cores on on boot and to support later revisions of the
specification.

Submitted by:	Robin Randhawa <Robin.Randhawa at ARM.com>
Sponsored by:	The FreeBSD Foundation
2015-04-12 13:00:58 +00:00
Andrew Turner
a3db11e053 Remove support for CPU_XSCALE_80200. None of our configs support it, and
there wasn;t an option to enable it.

While here remove a check for CPU_ARM10 being defined as it has also been
removed.
2015-03-30 09:29:45 +00:00
Andrew Turner
f855addb53 Only build cpufunc_asm_armv4.S when needed. 2015-03-30 08:37:03 +00:00
Andrew Turner
0ebebb1260 Build the cpufunc_asm_* files based on the cpu type, not which config file
we happen to be building.
2015-03-29 22:43:39 +00:00
Andrew Turner
9a25f3e847 Remove the bootconfig parsing. We never used it and always passed either an
empty string or NULL to the setup functions that called into it.
2015-03-29 20:37:28 +00:00
Bjoern A. Zeeb
54384e56c9 Remove all the handcrafted assembly in hwpmc_armv7.c and use the
common (autogenerated) versions.   Removes extra vertical space,
and makes it easier to grep for usage throughout the tree.
Conditionally compile only for arm6 [1] (yes sounds odd but is right).

Submitted by:	andrew [1]
Reviewed by:	gnn, andrew (ian earlier version I think)
Differential Revision: https://reviews.freebsd.org/D2159
Obtained from:	Cambridge/L41
Sponsored by:	DARPA, AFRL
2015-03-28 18:57:13 +00:00
Ian Lepore
84233ddb80 New pmap code for armv6. Disabled by default, option ARM_NEW_PMAP enables it.
This is pretty much a complete rewrite based on the existing i386 code.  The
patches have been circulating for a couple years and have been looked at by
plenty of people, but I'm not putting anybody on the hook as having reviewed
this in any formal sense except myself.

After this has gotten wider testing from the user community, ARM_NEW_PMAP
will become the default and various dregs of the old pmap code will be
removed.

Submitted by:	Svatopluk Kraus <onwahe@gmail.com>,
	  	Michal Meloun <meloun@miracle.cz>
2015-03-26 21:13:53 +00:00
Andrew Turner
aeca5b8bc9 Use the ARM unwinder with dtrace to extract the stack when asked. With this
dtrace is able to display a stack trace similar to the one below.

# dtrace -p 603 -n 'tcp:kernel::receive { stack(); }'
  0     70                         :receive
              kernel`ip_input+0x140
              kernel`netisr_dispatch_src+0xb8
              kernel`ether_demux+0x1c4
              kernel`ether_nh_input+0x3a8
              kernel`netisr_dispatch_src+0xb8
              kernel`ether_input+0x60
              kernel`cpsw_intr_rx+0xac
              kernel`intr_event_execute_handlers+0x128
              kernel`ithread_loop+0xb4
              kernel`fork_exit+0x84
              kernel`swi_exit
              kernel`swi_exit

Tested by:	gnn
Sponsored by:	ABT Systems Ltd
2015-02-19 12:20:21 +00:00
Andrew Turner
6da235a325 Pull the ARM ddb unwind code out to a new file. This will allow it to be
used by other places that expect to unwind the stack, e.g. dtrace and
stack(9).

As I have written most of this code I'm changing the license to the
standard FreeBSD license. I have received approval from the other
developers who have changed any of the affected code.

Approved by:	ian, imp, rpaulo, eadler (all license change)
2015-02-17 13:09:20 +00:00
Ruslan Bukin
6411d14d62 Add ARMv7 performance monitoring counters.
Differential Revision:	https://reviews.freebsd.org/D1687
Reviewed by:	rpaulo
Sponsored by:	DARPA, AFRL
2015-01-28 16:08:07 +00:00
Ian Lepore
7e55f8c198 Add a new trap-v6.c which has support for all armv7 exceptions. This
mostly paves the way for the new pmap code, and shouldn't result in any
noticible behavior differences.

Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
              Michal Meloun <meloun@miracle.cz
2015-01-03 22:33:18 +00:00
Ian Lepore
6c1d9637b7 Add cache maintenance functions which will be used by startup code to
initially set up the MMU.  Some day they may also be useful as part of
suspend/resume handling, when we get better at power management.

Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
              Michal Meloun <meloun@miracle.cz
2014-12-28 18:38:25 +00:00
Ian Lepore
2b71562fd8 Add new code to read and parse cpu identification data using the new CPUID
mechanism defined for armv7 (and also present on some armv6 chips including
the arm1176 used on rpi).  The information is parsed into a global cpuinfo
structure, which will be used by (upcoming) new cache and tlb maintenance
code to handle cpu-specific variations of the maintence sequences.

Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
              Michal Meloun <meloun@miracle.cz
2014-12-28 18:12:56 +00:00
Ian Lepore
7e96dec7bb Add ARMV6 as an arm option. This will cause obscure magic in config(8)
to automatically set the armv6 option when MACHINE_ARCH is armv6.  That
allows replacing ever-growing lists of cpu names as options to compile
a given file with the using either "optional armv6" or "optional !armv6".
2014-11-24 00:02:15 +00:00