Commit Graph

603 Commits

Author SHA1 Message Date
Andrew Turner
7b309274e3 Add the generic timer registers to sysreg.h and cpu-v6.h, and use the
access functions in the generic timer driver.

Differential Revision:	https://reviews.freebsd.org/D2198
Sponsored by:	The FreeBSD Foundation
2015-04-02 12:56:06 +00:00
Andrew Turner
a3db11e053 Remove support for CPU_XSCALE_80200. None of our configs support it, and
there wasn;t an option to enable it.

While here remove a check for CPU_ARM10 being defined as it has also been
removed.
2015-03-30 09:29:45 +00:00
Andrew Turner
303c8079ab Remove support for CPU_FA626TE. It's unused by any of our kernel configs. 2015-03-30 08:38:18 +00:00
Andrew Turner
37b25ee6f2 pj4b_config and pj4bv7_setup are only used when CPU_MV_PJ4B is defined. 2015-03-29 22:45:33 +00:00
Andrew Turner
930798f3a1 Remove arm1136 support. We don't have any configs that use it, and I don't
expect us to add support for any more arm11 SoCs.
2015-03-29 21:12:59 +00:00
Andrew Turner
9a25f3e847 Remove the bootconfig parsing. We never used it and always passed either an
empty string or NULL to the setup functions that called into it.
2015-03-29 20:37:28 +00:00
Andrew Turner
fd78c994f5 Remove ARM9_CACHE_WRITE_THROUGH, none of our configs define it. 2015-03-29 18:59:04 +00:00
Andrew Turner
6532862008 Remove unused cpufunc arm11 and armv6 code. While here only define the
remaining functions in the context we use them in.
2015-03-29 18:44:15 +00:00
Andrew Turner
c0fde778ab Remove unused arm10_* functions. The remaining functions are only used in
mv configs.
2015-03-29 17:42:32 +00:00
Andrew Turner
7a959e4944 Remove support for CPU_ARM10. No kernel configs could possibly use this as
it's not an available option. Along with this we will never support this
cpu type as very few arm10 chips were made.
2015-03-29 17:13:44 +00:00
Bjoern A. Zeeb
0ede88a413 Rather than defining our own magic checks here use INKERNEL() for
the PMC_IN_KERNEL() macro definition.

Add missing macros to extract the return address (LR) from the trapframe.

Discussed with:	andrew
Obtained from:	Cambridge/L41
Sponsored by:	DARPA, AFRL
MFC after:	2 weeks
2015-03-27 08:47:16 +00:00
Ian Lepore
84233ddb80 New pmap code for armv6. Disabled by default, option ARM_NEW_PMAP enables it.
This is pretty much a complete rewrite based on the existing i386 code.  The
patches have been circulating for a couple years and have been looked at by
plenty of people, but I'm not putting anybody on the hook as having reviewed
this in any formal sense except myself.

After this has gotten wider testing from the user community, ARM_NEW_PMAP
will become the default and various dregs of the old pmap code will be
removed.

Submitted by:	Svatopluk Kraus <onwahe@gmail.com>,
	  	Michal Meloun <meloun@miracle.cz>
2015-03-26 21:13:53 +00:00
Zbigniew Bodek
37143b98d4 Allow to override default kernel virtual address assignment on ARM
Each plaform performs virtual memory split between kernel and user space
and assigns kernel certain amount of memory space. However, is is sometimes
reasonable to change the default values. Such situation may happen on
systems where the demand for kernel buffers is high, many devices occupying
memory etc. This of course comes with the cost of decreasing user space
memory range so shall be used with care. Most embedded systems will not
suffer from this limtation but rather take advantage of this potential
since default behavior is left unchanged.

Submitted by:  Wojciech Macek <wma@semihalf.com>
Reviewed by:   imp
Obtained from: Semihalf
2015-03-20 10:15:34 +00:00
Ed Maste
371f621a11 Delete stray clause 3 and renumber. 2015-03-13 02:49:55 +00:00
Ian Lepore
a286c311ab Add minimum cache line sizes to struct cpuinfo, use them in the new cache
maintenance routines.  Also add a routine to invalidate the branch cache.

Submitted by:	Michal Meloun
2015-03-09 14:46:10 +00:00
Ian Lepore
d4047613ff Revert r279338. The casts are apparently bogus, despite the fact that
they've been working in i386 (where this change came from).
2015-03-02 20:40:25 +00:00
Ian Lepore
87ac2b4068 Add casting to make atomic ops work for pointers. (Apparently nobody has
ever done atomic ops on pointers before now on arm).

Submitted by:	Svatopluk Kraus <onwahe@gmail.com>
2015-02-26 23:05:46 +00:00
Ian Lepore
6baca8256b Correct a comment which was exactly backwards from reality. 2015-02-21 22:19:59 +00:00
Andrew Turner
1b23f9b9c3 Allow the ARM unwinder to work through modules. This will be used to add
support for unwinding from dtrace.

Tested by:	gnn (with dtrace)
Sponsored by:	ABT Systems Ltd
2015-02-19 12:06:57 +00:00
Andrew Turner
6da235a325 Pull the ARM ddb unwind code out to a new file. This will allow it to be
used by other places that expect to unwind the stack, e.g. dtrace and
stack(9).

As I have written most of this code I'm changing the license to the
standard FreeBSD license. I have received approval from the other
developers who have changed any of the affected code.

Approved by:	ian, imp, rpaulo, eadler (all license change)
2015-02-17 13:09:20 +00:00
George V. Neville-Neil
fcb5606706 Initial version of DTrace on ARM32.
Submitted by:	Howard Su based on work by Oleksandr Tymoshenko
Reviewed by:	ian, andrew, rpaulo, markj
2015-02-10 19:41:30 +00:00
Zbigniew Bodek
9fc0d68aeb Resolve cache line size from CP15
Switch the cache line size during invalidations/flushes
to be read from CP15 cache type register.

Submitted by:  Wojciech Macek <wma@semihalf.com>
Reviewed by:   ian, imp
Obtained from: Semihalf
2015-02-10 14:11:23 +00:00
Andrew Turner
8e35ef81cc Stop using load-multiple with lr and pc. This has been deprecated in ARMv7
and clang 3.6 warns about it. As this is used in libc and we build it with
-Werror this warning becomes an error stopping the build.
2015-01-31 19:55:12 +00:00
Ruslan Bukin
6411d14d62 Add ARMv7 performance monitoring counters.
Differential Revision:	https://reviews.freebsd.org/D1687
Reviewed by:	rpaulo
Sponsored by:	DARPA, AFRL
2015-01-28 16:08:07 +00:00
Ian Lepore
8436f7fe62 Declare Maxmem on arm. This should have been part of r277532. 2015-01-22 17:46:05 +00:00
Ian Lepore
ede35faed2 Micro-optimize the new arm inline bus_space implementation by grouping all
the data the inline functions access together at the start of the bus_space
struct.  The start-of part isn't so important, it's the grouping-together
that's the point: now all the most-accessed data should be in one cache line.

Suggested by:	  cognet
2015-01-21 20:12:35 +00:00
Ian Lepore
afe43c7b5f The versatile platform had two copies of a bus_space that are essentially
duplicates of the standard arm base bus_space, so just use it.
2015-01-21 04:06:36 +00:00
Ian Lepore
2737497b83 Move bs_unimplemented() to bus_space_generic.c so it can be shared. 2015-01-21 03:24:18 +00:00
Ian Lepore
4098ccafa4 Revise the arm bus_space implementation to avoid dereferencing the tag on
every operation to retrieve the bs_cookie value almost nothing actually uses.

The bus_space struct contains a private data pointer (poorly named bs_cookie,
now renamed to bs_privdata) which is used only by a few old armv4 xscale
implementations.  The bus_space functions were all defined to take this
value as the first parameter instead of the bus_space_tag_t, requiring all
the inline macro and function expansions to dereference the tag to pass it
to another function, which never uses it.  Now all the functions take the tag
as the first parameter and retrieve the privdata if they need it.

Also fix a couple bus_space_unmap() implementations that were calling
kva_free() instead of pmap_unmapdev().

Discussed with:	   cognet
2015-01-21 01:06:08 +00:00
Ian Lepore
16e2dc663f Add inline implementations of arm bus_space_read/write_N().
Reviewed by:	cognet
2015-01-20 22:56:59 +00:00
Andrew Turner
195237551a Add the User and PL1 read only and reqd write thread ID registers.
Sponsored by:	The FreeBSD Foundation
2015-01-20 11:11:32 +00:00
Ganbold Tsagaankhuu
d84d6e7716 Correct cpu type, it was rather Cortex A12 R0.
Approved by:    stas (mentor)
2015-01-14 01:23:50 +00:00
Ganbold Tsagaankhuu
cebf67b056 Add CPU ID for ARM Cortex A17.
Approved by:    stas (mentor)
2015-01-13 07:49:07 +00:00
Andrew Turner
3f53a2d612 Rename gic_init_secondary to arm_init_secondary_ic to help with the merge
of the arm_intrng project branch.
2015-01-11 16:46:43 +00:00
Ian Lepore
9326d90f0e Move the inclusion of cpu-v6.h inside the #ifdef _KERNEL block, so that
userland programs (which probably don't actually need machine/cpu.h) compile.
2015-01-08 03:59:03 +00:00
Ian Lepore
8a474d01ee Add accessors for the ARM CP15 performance monitor registers. Also ensure
that some #ifdef SMP code is also conditional on __ARM_ARCH >= 7; we don't
support SMP on armv6, but some drivers and modules are compiled with it
forced on via the compiler command line.
2015-01-08 01:28:46 +00:00
Mark Johnston
bdb9ab0dd9 Factor out duplicated code from dumpsys() on each architecture into generic
code in sys/kern/kern_dump.c. Most dumpsys() implementations are nearly
identical and simply redefine a number of constants and helper subroutines;
a generic implementation will make it easier to implement features around
kernel core dumps. This change does not alter any minidump code and should
have no functional impact.

PR:		193873
Differential Revision:	https://reviews.freebsd.org/D904
Submitted by:	Conrad Meyer <conrad.meyer@isilon.com>
Reviewed by:	jhibbits (earlier version)
Sponsored by:	EMC / Isilon Storage Division
2015-01-07 01:01:39 +00:00
Ian Lepore
7e55f8c198 Add a new trap-v6.c which has support for all armv7 exceptions. This
mostly paves the way for the new pmap code, and shouldn't result in any
noticible behavior differences.

Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
              Michal Meloun <meloun@miracle.cz
2015-01-03 22:33:18 +00:00
Ian Lepore
301e1601ad Fix alignment directives in arm asm code after clang 3.5 import.
The ancient gas we've been using interprets .align 0 as align to the
minimum required alignment for the current section.  Clang's integrated
assembler interprets it as align to a byte boundary.  Fortunately both
assemblers interpret a non-zero value as align to 2^N so just make sure
we have appropriate non-zero values everywhere.
2015-01-02 23:46:26 +00:00
Ed Maste
942c32333e Update ELF headers to include additional defines
The elftoolchain project includes these additional defines for various
userland programs. Given that arch-specific defines are still interesting
in the context of userland programs reading or writing ELF metadata, they
should be included in top-level ELF headers.

Remove duplicate defines from ARM and MIPS elf headers.

Submitted by:	will (initial version)
Reviewed by:	imp, will
Sponsored by:	The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D844
2015-01-02 15:36:29 +00:00
Ian Lepore
54f9ec883d Define a WFI macro that expands to the right form of wait-for-interrupt
depending on the architecture.
2015-01-01 23:18:37 +00:00
Ian Lepore
874d48dc8f Fix a "decl is not a prototype" error noticed by gcc (but not clang). 2014-12-28 19:05:32 +00:00
Ian Lepore
8d59f6c4da Eliminate an unused macro whose name clashes now with a function in the
new cpu-v6.h.  This should have been part of r276334.
2014-12-28 18:26:15 +00:00
Ian Lepore
518c6ac777 Add new TLB and cache maintainence functions for armv6 and armv7. These
are inline functions that handle all the routine maintenance operations
except the flush-all and invalidate-all routines which are required only
during early kernel init.

These inline functions should be very much faster than the old mechanism
that involved jumping through the big cpufuncs table, especially for
common operations such as invalidating a single TLB entry.  Note that
nothing is calling these yet, this just is just required infrastructure
for upcoming changes to the pmap-v6 code.
2014-12-28 18:19:05 +00:00
Ian Lepore
2b71562fd8 Add new code to read and parse cpu identification data using the new CPUID
mechanism defined for armv7 (and also present on some armv6 chips including
the arm1176 used on rpi).  The information is parsed into a global cpuinfo
structure, which will be used by (upcoming) new cache and tlb maintenance
code to handle cpu-specific variations of the maintence sequences.

Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
              Michal Meloun <meloun@miracle.cz
2014-12-28 18:12:56 +00:00
Ian Lepore
efa8bab713 Include acle-compat.h directly (we use its symbols) rather than getting
it via sysreg.h.
2014-12-26 14:29:27 +00:00
Ian Lepore
c93be3714d Define only the CP15 register operations that are valid for the architecture.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
              Michal Meloun <meloun@miracle.cz
2014-12-25 19:22:02 +00:00
Ian Lepore
eb4585bcc6 Add macros for asm barrier instructions with arch-specific implementations. 2014-12-25 19:08:39 +00:00
Ian Lepore
26659812e2 For data and instruction prefetch aborts, call the same handler in the C
code, passing a 0/1 flag that indicates which type of abort it was.  This
sets the stage for unifying the handling of page faults in a single routine.

Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
	      Michal Meloun <meloun@miracle.cz
2014-12-25 17:06:58 +00:00
Ian Lepore
b05d247e35 Create 'L' variants of all the ENTRY macros for file-static/local symbols.
If it seems like this is getting out of hand, I quite agree.  I wonder if
it's safe, here in the 21st century, to lose the distinction between C and
ASM symbols?
2014-12-25 16:49:33 +00:00