Commit Graph

311 Commits

Author SHA1 Message Date
Pyun YongHyeon
12c65daeaf Make sure to create DMA'able memory for statistics block. This was
missed in r212061 and it caused crashes for 570x controllers as
controller DMAed statistics to physical address 0.

Reported by:	kan
2010-09-07 18:29:29 +00:00
Pyun YongHyeon
175f87424f Remove unnecessary atomic operation in bge_poll. bge(4) always
holds a driver lock in the function entry and
memory synchronization is handled by bus_dmamap_sync(9).
2010-08-31 20:56:18 +00:00
Pyun YongHyeon
95a0a340f4 bge_txeof() already checks whether it has to free transmitted mbufs
or not by comparing reported TX consumer index with saved index. So
remove unnecessary check done after freeing transmitted mbufs.
While I'm here nuke unnecessary variable initializations.
2010-08-31 19:59:18 +00:00
Pyun YongHyeon
38cc61518b Handle PAE case correctly. You cannot effectively specify a 4GB
boundary in PAE case so use a 2GB boundary for PAE as suggested by
jhb.

Pointed out by:	jhb
Reviewed by:	jhb
2010-08-31 18:48:09 +00:00
Pyun YongHyeon
5b610048ec Split common parent DMA tag into ring DMA tag and TX/RX mbuf DMA
tag. All controllers that are not BCM5755 or higher have 4GB
boundary DMA bug. Previously bge(4) used 32bit DMA address to
workaround the bug(r199670). However this caused the use of bounce
buffers such that it resulted in poor performance for systems which
have more than 4GB memory. Because bus_dma(9) honors boundary
restriction requirement of DMA tag for dynamic buffers, having a
separate TX/RX mbuf DMA tag will greatly reduce the possibility of
using bounce buffers. For DMA buffers allocated with
bus_dmamem_alloc(9), now bge(4) explicitly checks whether the
requested memory region crossed the boundary or not.
With this change, only the DMA buffer that crossed the boundary
will use 32bit DMA address. Other DMA buffers are not affected as
separate DMA tag is created for each DMA buffer.
Even if 32bit DMA address space is used for a buffer, the chance to
use bounce buffer is still very low as the size of buffer is small.
This change should eliminate most usage of bounce buffers on
systems that have more than 4GB memory.

More correct fix would be teaching bus_dma(9) to honor boundary
restriction for buffers created with bus_dmamem_alloc(9) but it
seems that is not easy.

While I'm here cleanup bge_dma_map_addr() and remove unnecessary
member variables in bge_dmamap_arg structure.

Tested by:	marcel
2010-08-31 17:33:48 +00:00
Pyun YongHyeon
35f945cd62 It seems all Broadcom controllers have a bug that can generate UDP
datagrams with checksum value 0 when TX UDP checksum offloading is
enabled.  Generating UDP checksum value 0 is RFC 768 violation.
Even though the probability of generating such UDP datagrams is
low, I don't want to see FreeBSD boxes to inject such datagrams
into network so disable UDP checksum offloading by default.  Users
still override this behavior by setting a sysctl variable or loader
tunable, dev.bge.%d.forced_udpcsum.

I have no idea why this issue was not reported so far given that
bge(4) is one of the most commonly used controller on high-end
server class systems. Thanks to andre@ who passed the PR to me.

PR:	kern/104826
2010-08-22 01:39:09 +00:00
Pyun YongHyeon
7e32f79a44 Load tunable from loader.conf(5) instead of device.hints(5). 2010-08-21 23:13:16 +00:00
Pyun YongHyeon
caf088fc1f Use Miscellaneous Configuration Register bit definition instead of
magic number.
2010-07-15 23:34:58 +00:00
Pyun YongHyeon
a5ad2f1541 Remove enabling Data FIFO protection with indirect memory access.
r165114 added that code and that change ignored the same logic
committed in r135772. In addition, data FIFO protection should be
selectively enabled instead of applying to all PCIe devices.
While I'm here add BCM5785 to devices that do not require this
fix.
2010-07-14 21:47:49 +00:00
Pyun YongHyeon
736b931958 Prefer PCIR_BAR macro over BGE_PCI_BAR0. 2010-07-13 19:45:40 +00:00
Pyun YongHyeon
b65256d7bd Fix error message for jumbo buffer allocation failure. 2010-07-13 19:42:55 +00:00
Pyun YongHyeon
333704a37f style. 2010-07-13 19:39:51 +00:00
Pyun YongHyeon
797ab05ef6 Make bge_stop_fw() static.
While I'm here use ANSI function definitions.
2010-07-13 19:33:46 +00:00
Pyun YongHyeon
864104fe59 Zero entire status block and add missing bus_dmamap_sync(9). 2010-07-06 18:17:31 +00:00
Pyun YongHyeon
55a24a0597 It seems read DMA mode register requires both IPv4 TSO and IPv6 TSO
configuration to get IPv4 TSO work on BCM57780. While I'm here
apply the same fix to BCM5785 which shares similar hardware feature
of BCM57780. This change makes TSO work on BCM57780.

Tested by:	Tong Liu <nemoliu <> gmail dot com>
2010-07-06 02:07:59 +00:00
Pyun YongHyeon
77982948d1 Remove unused macros.
Reviewed by:	bde
2010-06-08 17:28:28 +00:00
Pyun YongHyeon
e0b7b101ce Fix a bug introduced in r199011. When bge(4) reuses loaded RX
buffers it should also reinitialize RX descriptors otherwise some
stale data could be passed to controller. This could end up with
mbuf double free or unexpected NULL pointer dereference in upper
stack. To fix the issue, save loaded buffer's length and
reinitialize RX descriptors with the saved value whenever bge(4)
reuses the loaded RX buffers.
While I'm here, increase the number of RX buffers to 512 from 256.
This simplifies RX buffer handling as well as giving more RX
buffers. Controller supports just fixed number of RX buffers
(i.e. 512) and bge(4) used to rely on hope that our CPU is fast
enough to keep up with the controller. With this change, bge(4)
will use 1MB for RX buffers but I don't think it would cause
problems in these days.

Reported by:	marcel
Tested by:	marcel
2010-06-05 23:29:24 +00:00
Marius Strobl
2d857b9b19 For the on-board interfaces found in Fujitsu SPARC64 machines obtain the
MAC address via OFW as well.
2010-04-26 18:56:06 +00:00
Pyun YongHyeon
d2b6e9a0bc Use pci_get_max_read_req() and pci_set_max_read_req() to set maximim
read request size.
2010-03-25 17:17:35 +00:00
Pyun YongHyeon
f584dfd113 Revert r205090.
It's hard to know when the mail box register write will get flushed to
the hardware and it may take longer.

Pointed out by:	scottl
2010-03-16 17:45:16 +00:00
Pyun YongHyeon
5e243d9a49 Reorder interrupt handler a bit such that producer/consumer
index of status block is read first before acknowledging the
interrupts. Otherwise bge(4) may get stale status block as
acknowledging an interrupt may yield another status block update.

Reviewed by:	marius
2010-03-12 18:18:04 +00:00
Pyun YongHyeon
fa8b4d63db Fix typo in r204978.
Pointed out by:	marius
2010-03-10 21:37:19 +00:00
Pyun YongHyeon
d896b3fe8d Fix typo in r204975.
Pointed out by:	marius
2010-03-10 20:55:55 +00:00
Pyun YongHyeon
cbb2b2fe3e Set maximum read byte count to 2048 for PCI-X BCM5703/5704 devices.
Also disable relaxed ordering as recommended by data sheet for
PCI-X devices. For PCI-X BCM5704, set maximum outstanding split
transactions to 0 as indicated by data sheet.
For BCM5703 in PCI-X mode, DMA read watermark should be less than
or equal to maximum read byte count configuration. Enforce this
limitation in DMA read watermark configuration.
2010-03-10 20:54:08 +00:00
Pyun YongHyeon
fbc374af79 Enable hardware fixes for BCM5704 B0 as recommended by data sheet. 2010-03-10 20:22:57 +00:00
Pyun YongHyeon
be95548d86 Disable TSO on BCM5755M controller until I understand better for
the issue. I still have no idea why TSO does not work on this
controller. davidch@ also confirmed there is no known TSO related
issues for this controller.
2010-02-26 22:29:42 +00:00
Pyun YongHyeon
5b355c4fb1 Remove Tx mbuf parsing code for VLAN in TSO path. Controller does
not support TSO over VLAN if VLAN hardware tagging is disabled so
there is no need to check VLAN here.
While I'm here make sure to pullup IP/TCP headers in the first
buffer.
2010-02-22 21:03:15 +00:00
Pyun YongHyeon
04bde8528b Add TSO support on VLAN. Controller requires VLAN hardware tagging
to make TSO work on VLAN. So if VLAN hardware tagging is disabled
explicitly clear TSO on VLAN. While I'm here remove duplicated
VLAN_CAPABILITIES call.
2010-02-20 23:21:06 +00:00
Pyun YongHyeon
4150ce6f17 Move device specific flag configuration to attach routine.
The softc obtained in device probe wouldn't be the same one used in
device attach. Drivers should not assume any values stored in softc
structure in probe routine will be available for its attach routine.
2010-02-09 19:12:06 +00:00
Pyun YongHyeon
9a6e301de2 PCI express device status register has W1C feature. Writing 0 has
no effect. Make sure to clear error bits by writing 1. [1]
While I'm here use predefined value instead of hardcodig magic
vlaue.

Submitted by:	msaitoh at NetBSD [1]
2010-02-01 20:58:45 +00:00
Pyun YongHyeon
d67eba2f3f Use new handshake command for BCM5750 or new controllers. 2010-01-22 18:46:37 +00:00
Pyun YongHyeon
899d684659 Fix a long standing ASF heartbeat sending bug. The initial
implementation of heartbeat interval was 2 but there was typo which
caused the heartbeat is sent approximately every 5 seconds. This
caused unintended controller reset by firmware because firmware
thought OS was crashed.

Submitted by:	Floris Bos < info <> je-eigen-domein dot nl >
Tested by:	Andrzej Tobola < ato <> iem dot pw dot edu dot pl >
2010-01-22 18:35:50 +00:00
Pyun YongHyeon
261f04d654 Don't free mbuf chains when bge(4) fails to collapse the mbuf
chains. This part of code is to enhance performance so failing the
collapsing should not free TX frames. Otherwise bge(4) will
unnecessarily drop frames which in turn can freeze the network
connection.

Reported by:	Igor Sysoev (is <> rambler-co dot ru)
Tested by:	Igor Sysoev (is <> rambler-co dot ru)
2010-01-15 17:55:18 +00:00
Pyun YongHyeon
ea3b412711 For controllers that has dual mode PHY(copper or fiber) interfaces
over GMII, make sure to enable GMII. With this change brgphy(4) is
used to handle the dual mode PHY. Since we still don't have a sane
way to pass PHY specific information to mii(4) layer special
handling is needed in brgphy(4) to determine which mode of PHY was
configured in parent interface.
This change make BCM5715S work.

Tested by:	olli
Obtained from:	OpenBSD
MFC after:	1 week
2010-01-14 19:08:43 +00:00
Xin LI
f7d1b2eb75 o Add PCI ID for BCM 5756.
o Don't enable BGE_FLAG_BER_BUG on both 5722 and 5756, and based
   on their PCI IDs rather than their chip IDs.

Reported by:	several PC-BSD users via kmoore
Reviewed by:	yongari, imp, jhb, davidch
Sponsored by:	iXsystems, Inc.
MFC after:	2 weeks
2010-01-13 22:39:39 +00:00
Pyun YongHyeon
4f4a16e152 Fix regression introduced in r198318. BCM5754/BCM5754M uses the
same ASIC ID of BCM5758 such that r198318 incorecctly enabled TSO
on BCM5754.BCM5754M controllers. BCM5754/BCM5754M needs a special
firmware to enable TSO and bge(4) does not support firmware based
TSO.

Reported by:	ed
Tested by:	ed
2010-01-03 21:49:24 +00:00
Pyun YongHyeon
beaa2ae169 Create sysctl node(dev.bge.%d.focred_collapse) instead of
hw.bge.forced_collapse. hw.bge.forced_collapse affects all bge(4)
controllers on system which may not desirable behavior of the
sysctl node. Also allow the sysctl node could be modified at any
time.

Reviewed by:	bde (initial version)
2009-12-08 17:54:23 +00:00
Pyun YongHyeon
9766cbd144 Partially revert r200228. For mini RCB case, bge(4) still have to
disable mini ring withtout regard to mini ring support.

Reported by:	marcel
Tested by:	marcel
2009-12-08 03:24:29 +00:00
Pyun YongHyeon
2a141b9412 Don't access jumbo frame related registers if controller lacks the
feature. These registers are reserved on controllers that have no
support for jumbo frame.
Only BCM5700 has mini ring so do not poke mini ring related
registers if controller is not BCM5700.

Reviewed by:	marius
2009-12-07 19:26:54 +00:00
Pyun YongHyeon
6fe124d275 Remove PHY isolate/power down code in bge_stop(). The isolation
handler in brgphy(4) does not exist and brgphy(4) just resets the
PHY and returns EINVAL as it has no isolation handler. I also agree
on Marius's opinion that stop handler of every NIC driver seems to
be the wrong place for implementing PHY isolate/power down.
If we need PHY isolate/power down it should be implemented in
brgphy(4) and users should administratively down the PHY.

Reviewed by:	marius
2009-12-07 19:18:23 +00:00
Pyun YongHyeon
d94f2b8506 Add workaround to overcome hardware limitation which allows only a
single outstanding DMA read operation. Most controllers targeted to
client with PCIe bus interface(e.g. BCM5761) may have this
limitation. All controllers for servers does not have this
limitation.
Collapsing mbuf chains to reduce number of memory reads before
transmitting was most effective way to workaround this. I got about
940Mbps from 850Mbps with mbuf collapsing on BCM5761. However it
takes a lot of CPU cycles to collapse mbuf chains so add tunable to
control the number of allowed TX buffers before collapsing. The
default value is 0 which effectively disables the forced collapsing.
For most cases 2 would yield best performance(about 930Mbps)
without much sacrificing CPU cycles.
Note the collapsing is only activated when the controller is on
PCIe bus and the frame does not need TSO operation. TSO does not
seem to suffer from the hardware limitation because the payload
size is much bigger than normal IP datagram.
Thanks to davidch@ who told me the limitation of client controllers
and actually gave possible workarounds to mitigate the limitation.

Reviewed by:	davidch, marius
2009-12-03 23:57:06 +00:00
Pyun YongHyeon
6a15578d8a Fix typo which inversed the logic which in turn disabled MSI.
Pointy hat to:  yongari
2009-11-25 17:51:14 +00:00
Pyun YongHyeon
7e6acdf12b Make sure one shot MSI is enabled.
Submitted by:	marius
2009-11-25 17:30:38 +00:00
Pyun YongHyeon
fd4d32feb2 BGE_FLAG_40BIT_BUG should be set before creating DMA tags.
Pointy hat to:  yongari
2009-11-24 17:46:58 +00:00
Pyun YongHyeon
30f57f615b Reduce status block size DMAed by controller. bge(4) uses single
Tx/Rx/Rx return ring such that large part of status block was not
used at all. All bge(4) controllers except BCM5700 AX/BX has a
feature to control the size of status block. So use minimum status
block size allowed in controller. This reduces number of DMAed
status block size to 32 bytes from 80 bytes.
2009-11-22 21:45:55 +00:00
Pyun YongHyeon
2e1d4df419 Add missing function prototype in r199671. 2009-11-22 21:20:26 +00:00
Pyun YongHyeon
ca3f1187f1 Implement TSO for BCM5755 or newer controllers. Some controllers
seem to require a special firmware to use TSO. But the firmware is
not available to FreeBSD and Linux claims that the TSO performed by
the firmware is slower than hardware based TSO. Moreover the
firmware based TSO has one known bug which can't handle TSO if
ethernet header + IP/TCP header is greater than 80 bytes. The
workaround for the TSO bug exist but it seems it's too expensive
than not using TSO at all. Some hardwares also have the TSO bug so
limit the TSO to the controllers that are not affected TSO issues
(e.g. 5755 or higher).
While I'm here set VLAN tag bit to all descriptors that belengs to
a frame instead of the first descriptor of a frame. The datasheet
is not clear how to handle VLAN tag bit but it worked either way in
my testing. This makes it simplify TSO configuration a little bit.

Big thanks to davidch@ who sent me detailed TSO information.
Without this I was not able to implement it.

Tested by:	current
2009-11-22 21:16:30 +00:00
Pyun YongHyeon
f681b29a6d Fix two long standing bugs on bge(4). Most pre BCM5755 controllers
have a DMA bug when buffer address crosses a multiple of the 4GB
boundary(e.g. 4GB, 8GB, 12GB etc). Limit DMA address to be within
4GB address for these controllers. The second DMA bug limits DMA
address to be within 40bit address space. This bug applies to
BCM5714 and BCM5715 and 5708(bce(4) controller). This is not
actually a MAC controller bug but an issue with the embedded PCIe
to PCI-X bridge in the device. So for BCM5714/BCM5715 controllers
also limit the DMA address to be within 40bit address space.
Special thanks to davidch@ who gave me detailed errata information.
I think this change will fix long standing bge(4) instability
issues on systems with more than 4GB memory.

Reviewed by:	davidch
2009-11-22 20:50:27 +00:00
Pyun YongHyeon
dfe0df9a76 For MSI case, interrupt is not shared and we don't need to force
PCI flush to get correct status block update. Add an optimized
interrupt handler that is activated for MSI case. Actual interrupt
handling is done by taskqueue such that the handler does not
require driver lock for Rx path. The MSI capable bge(4) controllers
automatically disables further interrupt once it enters interrupt
state so we don't need PIO access to disable interrupt in interrupt
handler.
2009-11-22 20:31:40 +00:00
Pyun YongHyeon
b9c05fa593 Cache Rx producer/Tx consumer index as soon as we know status block
update and then clear status block. Previously it used to access
these index without synchronization which may cause problems when
bounce buffers are used. Also add missing bus_dmamap_sync(9) in
polling handler. Since we now update status block in driver, adjust
bus_dmamap_sync(9) for status block.
2009-11-22 20:02:13 +00:00