settings as exported via the ACPI _PSS method. OEMs use this interface
to encapsulate chipset or processor-specific methods (e.g., SpeedStep or
Powernow) and export their settings in a standard way. On systems that
have valid ACPI Performance states and a hardware-specific driver (e.g.,
ichss), acpi_perf(4) is preferred.
release) the sio spin mutex, as use of synchronization primitives in
the debugger can result in substantial problems. With this patch in
place entering the debugger via a serial console is made
substantially more reliable.
MFC after: 1 week
Tested by: kris
Discussed with: bde
The cause of "Duplicate mbuf free panic" is in the programming
error of hme_load_txmbuf(). The code path of the panic is the
following.
1. Due to unknown reason DMA engine was freezed. So TX descritors
of HME become full and the last failed attempt to transmit a
packet had set its associated mbuf address to hme_txdesc
structure. Also the failed packet is requeued into interface
queue structure in order to retrasmit it when there are more
available TX descritors.
2. Since DMA engine was freezed, if_timer starts to decrement its
counter. When if_timer expires it tries to reset HME. During
the reset phase, hme_meminit() is called and it frees all
associated mbuf with descriptors. The last failed mbuf is also
freed here.
3. After HME reset completed, HME starts to retransmit packets
by dequeing the first packet in interface queue.(Note! the
packet was already freed in hme_meminit()!)
4. When a TX completion interrupt is posted by the HME, driver
tries to free the successfylly transmitted mbuf. Since the
mbuf was freed in step2, now we get "Duplicate mbuf free panic".
However, the real cause is in DMA engine freeze. Since no fatal
errors reported via interrupts, there might be other cause of
the freeze. I tried hard to understand the cause of DMA engine
freeze but couldn't find any clues. It seems that the freeze
happens under very high network loads(e.g. 7.5-8.0 MB/s TX speed).
Though this fix is not enough to eliminate DMA engine freeze it's
better than panic.
Reported by: jhb via sparc64 ML
CIS, weren't actually used anywhere (other than the generic PC Card
code when certain variables are defined). They aren't used in NetBSD
either. Make things simpler by removing them. Change PLANEX_2 to
PLANEX and tweak wi and owi to use that instead. The PLANEX id seems
to actually be pci ID assigned to planex, not its pcmcia id. Ooops.
I don't know if this is a reporting error from where this entry came
from, or if it is a mistake on PLANEX's part. I suspect the latter,
as ACTIONTEC and NEWMEDIA made the same mistake (although new media
may be because it uses an advansys chip inside). Make a note of this
in the file. The 0xc entires may be JEITA assigned, so note that as
well.
# This leaves just 3 entries that are totally unknown: airvast, archos
# and edimax although the arivast number is the same assigned to
# avertec in usb...
This driver implements "unaddressed listen only mode", which is what
printers and plotters commonly do on GP-IB busses.
This means that you can capture print/plot like output from your
instruments by configuring them as necessary (good luck!) and
cat -u /dev/gpib0l > /tmp/somefile
Since there is no way to know when no more output is comming you
will have to ctrl-C the cat process when it is done (that is why
the -u is important).
The presence or absence of a keyboard does not change whether an
UART is designed as a keyboard port or not and thus whether we
can use the port as a TTY or not.
We now call sunkbd_attach() even when we didn't previously find
a keyboard. Emit a useful message stating that no keyboard was
found, but don't do anything else.
MFC after: 5 days
ServeRAID 4 - 7 models right now. Support for older cards is possible, but
I don't have any hardware to experiment with.
Thanks to Jack Hammer at Adaptec for providing debugging hints.
Sponsored by: ImproWare AG, Switzerland
engineering the pending interrupt sources from the current
state of the controller. For channel A we can always read the
interrupt pending register (RR3). For channel B we can read
the interrupt vector register (RR2) because it contains the
modified vector and thus includes the interrupt source.
Since we currently need puc(4) for the Z8530, we know that
the interrupt handler for both channels will be called and
thus that RR3 will always be read at least once, even if ch A
has no pending interrupt.
NOTE: The modified interrupt vector has no value that represent
a lack of pending interrupt for channel B. That is, the
value read when no interrupts are pending is the same as the
value for the special receive condition. Fortunately, we don't
actually have to depend on that interrupt source. This does
mean that we need to properly handle the overflow condition,
when we read received character from the chip.
o The DSR signal is represented by the SYNC bit in the external
status register (RR0). We now properly track DSR.
o It's save to enable the external/status interrupt source. We
now get interrupts when line signals (DSR, DCD or CTS) change.
Problems fixes:
o interrupt storms.
o blocked open(2).
o lack of (hardware) flow control.
o unable to report DSR.
MFC after: 5 days
providing special version of CDIOCREADSUBCHANNEL ioctl(), which assumes that
result has to be placed into kernel space not user space. In the long run
more generic solution has to be designed WRT emulating various ioctl()s
that operate on userspace buffers, but right now there is only one such
ioctl() is emulated, so that it makes little sense.
MFC after: 2 weeks
thought. I'm unsure why I thought this was the case, but it
definitely isn't for this card. If another card with the other ID
makes an appearance, then we'll add a second entry for it.
# With this change my Olicom OC2220 is now working again, since I make
# this commit with that device. :-)
EtherJet, the interrupt is selected in the eeprom based on the layout
of the PC Card board. Since this is encoded into the EEPROM, and has
no relationship to the IRQ that the pccard bridge routes the PC Card's
interrupt pin to.
As such, stop writing to that register. This gets my EtherJet working.
# The eeprom reading code appears to be totally wrong for my EtherJet
# card. This causes the card to bogusly detect the media options
# available.
significant clean up and optimizations:
- don't call bioq_disksort() on every command, the hardware will do that for
us.
- remove all of the complicated bio deferral code. bio's that can't be
serviced immediately can just wait on the bioq.
- Only reserve one command object for doing control commands to the card.
This simplifies a lot of code and significantly reduces the size of the
command struct.
- Allocate commands out of a slab instead of embedding them into the softc.
- Call the command action method directly instead of having ips_get_free_cmd()
call it indirectly.
MFC After: 1 week
null-modem tty device emulate the speed settings faithfully.
The speed is emulated independently for the two directions, using
the slower of the local sides ispeed and the remote sides ospeed.
The emulated speed takes settings of bits/char, parity and stopbit
into account.
Inspired by: The BSD-DK Editor Celebrity Deathmatch Contest
the interface when going to toggle VLAN support for
internal reasons. If the IFCAP_VLAN_HWTAGGING bit is
cleared, we should rely on the (re)init routine to turn
VLAN support off and never touch the relevant hardware bits.
This applies to other capability bits, too. The user
obviously has a reason for clearing a capability bit,
e.g., if his particular NIC is buggy and hangs if a
certain hardware capability is turned on even for a
fraction of a second.
The flag adapter->em_insert_vlan_header still is set or
reset irrespective of the IFCAP_VLAN_HWTAGGING setting,
as before, in order to handle the case when a user sets
promiscuous mode on an interface first and later turns
its IFCAP_VLAN_HWTAGGING bit on.
This change might look orthogonal to rev#1.85, but in fact
it is not. It introduces bugfixes that hopefully will make
implementing the general scheme mentioned in the commit
message of rev#1.85 easier.
configuration: it appears to work properly in the non-promiscuous case, but
we've not yet implemented a more general solution that maintains full
functionality with promiscuous mode enabled. While my hope is that we can
get one implemented soon, this will improve functionality substantially in
the mean time.
MFC after: 3 days
