Commit Graph

716 Commits

Author SHA1 Message Date
Jake Burkholder
07a312f6b6 Use memset instead of __builtin_memset. Apparently there's an inline
memset in libkern which causes problems; why that's there is beyond me.
2002-12-29 08:37:11 +00:00
Jake Burkholder
bc4ede2030 Use the meaningful mnemonics for ancillary state registers now that gas
is invoked properly to understand them.

	%asr19 -> %gsr
	%asr20 -> %set_softint
	%asr21 -> %clear_softint
2002-12-29 00:23:48 +00:00
Jake Burkholder
418a8ca992 Forgot this file in previous commit. 2002-12-28 23:58:18 +00:00
Jake Burkholder
af13cb9f11 - Moved storing %g1-%g5 in the trapframe until after interrupts are enabled.
- Restore %g6 and %g7 for kernel traps if we are returning to prom code.
  This allows complex traps (ones that call into C code) to be handled from
  the prom.
2002-12-28 23:57:52 +00:00
Jake Burkholder
63100290f3 Pass 0 in %o1 to tl0_trap for all non-interrupt traps. This will be used
to pass the pil when tl0_trap also handles interrupts.
2002-12-28 23:34:21 +00:00
Alan Cox
472c3b6f4f Hold the page queues lock around calls to vm_page_flag_clear() and
vm_page_wakeup().
2002-12-28 21:14:44 +00:00
Alan Cox
fca5d6baba Use VM_ALLOC_WIRED in pmap_pinit(). 2002-12-28 08:10:29 +00:00
Jake Burkholder
7b666b648f Define UMA_MD_SMALL_ALLOC so that uma_small_alloc and uma_small_free will
be used for zones that allocate objects of less 1 page.  The biggest advantage
of this is that all of a sudden the majority of kernel malloc-ed data doesn't
need kva allocated for it.  Besides microbenchmarks I haven't seen a measurable
performance improvement from doing this.
2002-12-27 19:31:26 +00:00
Jake Burkholder
66a6d547ec Teach /dev/kmem about direct mapped addresses.
Note that a better solution for how to make kernacc work for direct mapped
addresses is needed for all platforms that use them.
2002-12-27 19:18:04 +00:00
Jake Burkholder
9ff9f0fb80 Implement uma_small_alloc and uma_small_free. Not yet used. 2002-12-27 03:11:29 +00:00
Jake Burkholder
885f001d98 - Use direct mapped addresses for the message buffer, for the crash dump
mappings, and for pmap_map which is used to map the vm_page structures.
- Don't allocate kva space for any of the above.
2002-12-27 01:50:29 +00:00
Jake Burkholder
a106c6930a - Change the way the direct mapped region is implemented to be generally
useful for accessing more than 1 page of contiguous physical memory, and
  to use 4mb tlb entries instead of 8k.  This requires that the system only
  use the direct mapped addresses when they have the same virtual colour as
  all other mappings of the same page, instead of being able to choose the
  colour and cachability of the mapping.
- Adapt the physical page copying and zeroing functions to account for not
  being able to choose the colour or cachability of the direct mapped
  address.  This adds a lot more cases to handle.  Basically when a page has
  a different colour than its direct mapped address we have a choice between
  bypassing the data cache and using physical addresses directly, which
  requires a cache flush, or mapping it at the right colour, which requires
  a tlb flush.  For now we choose to map the page and do the tlb flush.

This will allows the direct mapped addresses to be used for more things
that don't require normal pmap handling, including mapping the vm_page
structures, the message buffer, temporary mappings for crash dumps, and will
provide greater benefit for implementing uma_small_alloc, due to the much
greater tlb coverage.
2002-12-23 23:39:57 +00:00
Jake Burkholder
dcedf26597 - Fix a bug where the faulting address for an mmu miss could sometimes be
clobbered due to some debug code.  This was harmless and just superfluous
  soft faults.
- Update some comments.
2002-12-23 02:18:45 +00:00
Jake Burkholder
950002bf92 - Rearrange pmap_bootstrap slightly to be more in dependency order.
- Put the kernel tsb before before the kernel load address, below
  VM_MIN_KERNEL_ADDRESS, instead of after the kernel where it consumes
  usable kva.  This is magic mapped so the virtual address is irrelevant,
  it just needs to be out of the way.
2002-12-22 23:01:14 +00:00
Jake Burkholder
c3c2862df4 - Add a spin lock to single thread cache invalidation and tlb flush ipis,
which allows ipis to be sent outside of Giant.
- Remove the ap boot mutex, which is unused.
2002-12-22 20:50:23 +00:00
Tim J. Robbins
b30a7779d4 MB_LEN_MAX is not MD, move it to the MI limits.h. 2002-12-22 06:38:45 +00:00
Jake Burkholder
b8eb0267c0 - Add a pmap pointer to struct md_page, and use this to find the pmap that
a mapping belongs to by setting it in the vm_page_t structure that backs
  the tsb page that the tte for a mapping is in.  This allows the pmap that
  a mapping belongs to to be found without keeping a pointer to it in the
  tte itself.
- Remove the pmap pointer from struct tte and use the space to make the
  tte pv lists doubly linked (TAILQs), like on other architectures.  This
  makes entering or removing a mapping O(1) instead of O(n) where n is the
  number of pmaps a page is mapped by (including kernel_pmap).
- Use atomic ops for setting and clearing bits in the ttes, now that they
  return the old value and can be easily used for this purpose.
- Use __builtin_memset for zeroing ttes instead of bzero, so that gcc will
  inline it (4 inline stores using %g0 instead of a function call).
- Initially set the virtual colour for all the vm_page_ts to be equal to their
  physical colour.  This will be more useful once uma_small_alloc is
  implemented, but basically pages with virtual colour equal to phsyical
  colour are easier to handle at the pmap level because they can be safely
  accessed through cachable direct virtual to physical mappings with that
  colour, without fear of causing illegal dcache aliases.

In total these changes give a minor performance improvement, about 1%
reduction in system time during buildworld.
2002-12-21 22:43:19 +00:00
Jake Burkholder
e43e24711b Make pmap_qenter and pmap_qremove look more like the other pmaps. 2002-12-21 10:44:30 +00:00
Jake Burkholder
fabf7ce58c Removed unused pmap_qenter_flags. 2002-12-21 10:04:14 +00:00
Jake Burkholder
fe1998ec51 Make the atomic arithmetic functions return the old value, since they're
all implemented with cas anyway.
2002-12-21 08:53:26 +00:00
Jake Burkholder
9830739b64 Add page queue locking around functions that call vm_page_flag_set. This
fixes a failed assertion early in boot on sparc64.

Reported by:	Roderick van Domburg <r.s.a.vandomburg@student.utwente.nl>
2002-12-20 21:47:21 +00:00
Julian Elischer
696058c3c5 Unbreak the KSE code. Keep track of zobie threads using the Per-CPU storage
during the context switch. Rearrange thread cleanups
to avoid problems with Giant. Clean threads when freed or
when recycled.

Approved by:	re (jhb)
2002-12-10 02:33:45 +00:00
Thomas Moestl
a9dace022e Exclude yet more interrupt mapping registers from the OBIO INO search,
namely the ones for the timers, error handling and power management.
The registers for the timers, power management and PCI bus b errors are
reserved on Sabres (US-IIi) and can lead to false matches there.
Since all of them are never used for devices on the bus, they can be omitted
safely.

Approved by:	re
2002-12-06 13:16:52 +00:00
Thomas Moestl
df9f4fead8 Remove a workaround for a binutils bug that was fixed in the recent
import, as it breaks the relocation kernel modules built with the new
binutils.
Note that this, together with the binutils import, marks a kernel module
flag day on sparc64: modules built with the old binutils will not work
with new kernels and vice versa. Mismatches will result in panics.

Approved by:	re
2002-12-02 18:56:30 +00:00
Thomas Moestl
f57d04ab1d Always initialize the UPA target module id in the interrupt mapping
register to the one of the processor doing the interrupt setup. This
is required since this field is preinitialized to 0, but there exist
machines which have no processor with a MID of 0 (e.g. e450s with 1 or 2
processors).

Add some more macros for handle the interrupt mapping registers, and
rename some existing ones for consistency.

Approved by:	re
2002-12-01 23:30:26 +00:00
Thomas Moestl
0aa267f6a7 1.) Do not look for PCI INOs in the FFB interrupt mapping registers; they
are nevers used for PCI interrupts, but can cause false matches since
    they are fully programmable.
2.) Skip the mapping registers for slot a2 and a3 on "psycho" bridges,
    since they are not present there. Again, this could cause false matches,
    which would result in the interrupt being delivered at most once.

Submitted by:	jake (2)
Approved by:	re
2002-12-01 23:21:15 +00:00
Thomas Moestl
bb4c2b1298 Remove some long-dead cruft in the interrupt handling code which was
never used in FreeBSD.

Approved by:	re
2002-12-01 23:13:59 +00:00
Thomas Moestl
ed2f312db5 Reverse the quirk table entry for swizzling on a missing interrupt map;
this is now done on all machines except for some known problematic ones.

Add an additional guard to make sure that the interrupt numbers are
in the correct range before swizzling. This should catch any remaining
models for which the swizzle is inappropriate.

Correct the swizzle calculation to account for the fact that the parent
interrupt numbers to be swizzled are 1-based.

Approved by:	re
2002-12-01 23:06:14 +00:00
Thomas Moestl
d4523ab223 Fix some comments describing psycho registers.
Approved by:	re
2002-12-01 23:00:41 +00:00
Thomas Moestl
fe4c53992a Do not panic when a dmamap is unloaded more then once, but just silently
ignore it. This is non-fatal on the other architectures, and some
drivers seem to do this.

Approved by:	re
2002-12-01 22:59:29 +00:00
Alan Cox
8f2ea21450 Add page queues locking to vunmapbuf().
Approved by:	re (blanket)
2002-11-24 21:13:34 +00:00
Maxime Henrion
b19d9defef Under certain circumstances, we were calling kmem_free() from
i386 cpu_thread_exit().  This resulted in a panic with WITNESS
since we need to hold Giant to call kmem_free(), and we weren't
helding it anymore in cpu_thread_exit().  We now do this from a
new MD function, cpu_thread_dtor(), called by thread_dtor().

Approved by:	re@
Suggested by:	jhb
2002-11-22 23:57:02 +00:00
John Baldwin
69da428022 Fix compile in the case of SMP defined but DDB not defined.
Approved by:	re (implicit, DP2 doesn't build w/o this)
2002-11-20 14:09:33 +00:00
Jake Burkholder
42f850516c Run configure at SI_SUB_THIRD instead of SI_SUB_ANY like other
architectures.
2002-11-18 03:28:23 +00:00
Jake Burkholder
7446769caf MFi386 r1.369. Clear the PG_WRITEABLE flag in pmap_clear_write; return
immediately if its already clear.

Suggested by:	alc
2002-11-17 01:17:07 +00:00
Daniel Eischen
2be05b70c9 Add getcontext, setcontext, and swapcontext as system calls.
Previously these were libc functions but were requested to
be made into system calls for atomicity and to coalesce what
might be two entrances into the kernel (signal mask setting
and floating point trap) into one.

A few style nits and comments from bde are also included.

Tested on alpha by: gallatin
2002-11-16 06:35:53 +00:00
Thomas Moestl
222e92877c Don't register the powerfail interrupt as fast in the
non-DEBUGGER_ON_POWERFAIL case so that shutdown_nice() can be called
without problems.

Reported & tested by:	Gavin Atkinson <gavin@ury.york.ac.uk>
2002-11-14 11:29:16 +00:00
Alan Cox
eea85e9bb6 Move pmap_collect() out of the machine-dependent code, rename it
to reflect its new location, and add page queue and flag locking.

Notes: (1) alpha, i386, and ia64 had identical implementations
of pmap_collect() in terms of machine-independent interfaces;
(2) sparc64 doesn't require it; (3) powerpc had it as a TODO.
2002-11-13 05:39:58 +00:00
Alan Cox
6372d61e3e - Clear the page's PG_WRITEABLE flag in the i386's pmap_changebit()
if we're removing write access from the page's PTEs.
 - Export pmap_remove_all() on alpha, i386, and ia64.  (It's already
   exported on sparc64.)
2002-11-11 05:17:34 +00:00
Thomas Moestl
f7f33d6984 Remove physmem from here, too, as it is defined in vm_init.c since
r1.35 (forgotten in my last commit due to a botched patch).

Pointy hat to:	tmm
2002-11-08 11:10:50 +00:00
Thomas Moestl
8c8a1169df Add two new workaround for firmware anomalies:
1. At least some Netra t1 models have PCI buses with no associated
   interrupt map, but obviously expect the PCI swizzle to be done with
   the interrupt number from the higher level as intpin. In this case,
   the mapping also needs to continue at parent bus nodes.
   To handle that, add a quirk table based on the "name" property of
   the root node to avoid breaking other boxen. This property is now
   retrieved and printed at boot.
2. On SPARCengine Ultra AX machines, interrupt numbers are not mapped
   at all, and full interrupt numbers (not just INOs) are given in
   the interrupt properties. This is more or less cosmetical; the
   PCI interrupt numbers would be wrong, but the psycho resource
   allocation method would pass the right numbers on anyway.

Tested by:	mux (1), Maxim Mazurok <maxim@km.ua> (2)
2002-11-07 16:07:46 +00:00
Maxime Henrion
f3595051aa s/HZ/Hz/ 2002-11-06 23:31:01 +00:00
Juli Mallett
751d91aabd Remove what was a temporary bogus assignment of bits of siginfo_t, as it does
not look like the prerequisites to fill it in properly will be in the tree
for the upcoming release, but it's mostly done, so there is no need for these
to stay around to remind us.
2002-11-06 14:53:35 +00:00
Jake Burkholder
1bc796d774 Don peril sensitive sun glasses and change the default system call vector
for sparc64 from trap #9 to trap #65.  This is one of the ABI "blessed"
system call vectors and is different from any other system that we might
want to emulate, making the emulation easier by reducing the number of
code paths that need to be shared.  Compatibility with old applications
is provided with COMPAT_FREEBSD4.
Add defines for a few special traps that we may need to implement for
compatibility with 32bit applications, and add comments on which vectors
are used for what in other systems, and which are available.
Pass magic flags to trap() for deprecated or unimplemented system call
vectors so they will deliver SIGSYS instead of SIGILL.

This piggy backs nicely with the recent sigaction(2) system call number
change, and provided the rules are followed for upgrading past it, this
change should not be noticed.
2002-10-27 17:22:43 +00:00
Jake Burkholder
8d9faed03e Allow deprecated or unimplemented system call vectors to deliver SIGSYS,
as suggested by the sparc v9 ABI.
2002-10-26 17:38:20 +00:00
Jake Burkholder
5b412c08c2 Remove an unused macro. 2002-10-26 17:36:37 +00:00
Peter Wemm
c69d7e2f4f Add COMPAT_FREEBSD4 for the transition. COMPAT_43 was already present. 2002-10-26 04:57:19 +00:00
Peter Wemm
23eeeff7be Split 4.x and 5.x signal handling so that we can keep 4.x signal
handling clean and functional as 5.x evolves.  This allows some of the
nasty bandaids in the 5.x codepaths to be unwound.

Encapsulate 4.x signal handling under COMPAT_FREEBSD4 (there is an
anti-foot-shooting measure in place, 5.x folks need this for a while) and
finish encapsulating the older stuff under COMPAT_43.  Since the ancient
stuff is required on alpha (longjmp(3) passes a 'struct osigcontext *'
to the current sigreturn(2), instead of the 'ucontext_t *' that sigreturn
is supposed to take), add a compile time check to prevent foot shooting
there too.  Add uniform COMPAT_43 stubs for ia64/sparc64/powerpc.

Tested on: i386, alpha, ia64.  Compiled on sparc64 (a few days ago).
Approved by: re
2002-10-25 19:10:58 +00:00
Thomas Moestl
db44ef5176 Initialize tick_MHz and related variables much earlier. After the last
revision of tick.c, this was done at SI_SUB_CLOCKS, which is too late
because tick_MHz is required for DELAY() to work.

Reviewed by:	jake
2002-10-25 17:42:14 +00:00
Thomas Moestl
736b63df0d Fix iommu_dvmamap_sync() to use the right address when flushing the
streaming cache. This bug could have the potential to cause data
corruption on systems with Psycho U2P bridges (Sabre bridges have no
streaming cache).
However, due to the usual driver architecture, it is believed that
corruption did occur only in rare cases (if at all).
2002-10-25 17:31:31 +00:00