Commit Graph

37 Commits

Author SHA1 Message Date
Zbigniew Bodek
c4b8fcd66c Add new CP15 operations and DB_SHOW_COMMAND to print CP15 registers
Submitted by:   Wojciech Macek <wma@semihalf.com>
Reviewed by:    imp, Michal Meloun <meloun@miracle.cz>
Obtained from:  Semihalf
2015-05-06 15:17:28 +00:00
Zbigniew Bodek
9fc0d68aeb Resolve cache line size from CP15
Switch the cache line size during invalidations/flushes
to be read from CP15 cache type register.

Submitted by:  Wojciech Macek <wma@semihalf.com>
Reviewed by:   ian, imp
Obtained from: Semihalf
2015-02-10 14:11:23 +00:00
Ganbold Tsagaankhuu
d84d6e7716 Correct cpu type, it was rather Cortex A12 R0.
Approved by:    stas (mentor)
2015-01-14 01:23:50 +00:00
Ganbold Tsagaankhuu
cebf67b056 Add CPU ID for ARM Cortex A17.
Approved by:    stas (mentor)
2015-01-13 07:49:07 +00:00
Ian Lepore
7e55f8c198 Add a new trap-v6.c which has support for all armv7 exceptions. This
mostly paves the way for the new pmap code, and shouldn't result in any
noticible behavior differences.

Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
              Michal Meloun <meloun@miracle.cz
2015-01-03 22:33:18 +00:00
Andrew Turner
b8fd1e31d9 Unify interrupts bit definition and usage. While here remove PSR_C_bit.
Submitted by:	Svatopluk Kraus <onwahe at gmail.com>,
		Michal Meloun <meloun at miracle.cz>
Differential Revision: https://reviews.freebsd.org/D754
2014-09-10 15:25:15 +00:00
Andrew Turner
d7f129a3cb Add more register values to armreg.h and remove CPU_CONTROL_32BP_ENABLE
from asm.h as they were already defined in armreg.h.

Submitted by:	Michal Meloun <meloun at miracle.cz>
2014-09-10 13:38:52 +00:00
Ruslan Bukin
66e227bf1e Add Cortex-A15 cpu id revisions. 2014-04-01 04:56:40 +00:00
Ian Lepore
a297028904 Remove all traces of support for ARM chips prior to the arm9 series. We
never actually ran on these chips (other than using SA1 support in an
emulator to do the early porting to FreeBSD long long ago).  The clutter
and complexity of some of this code keeps getting in the way of other
maintenance, so it's time to go.
2014-03-09 21:12:31 +00:00
Ian Lepore
255a0cc653 Use the right symbols for determining arm architecture. Include the
necessary header file which has the new FAULT_WNR symbol defined in it.
2014-02-12 19:59:30 +00:00
Ganbold Tsagaankhuu
543c9e95f2 Add identification and necessary type checks for Krait CPU cores. Krait CPU is used in
Qualcomm Snapdragon S4 and Snapdragon 400/600/800 SoCs and has architectural
similarities to ARM Cortex-A15. As for development boards IFC6400 series embedded
boards from Inforce Computing uses Snapdragon S4 Pro/APQ8064.

Approved by: stas (mentor)
2013-12-20 00:56:23 +00:00
Eitan Adler
7a22215c53 Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this
shifts into the sign bit.  Instead use (1U << 31) which gets the
expected result.

This fix is not ideal as it assumes a 32 bit int, but does fix the issue
for most cases.

A similar change was made in OpenBSD.

Discussed with:	-arch, rdivacky
Reviewed by:	cperciva
2013-11-30 22:17:27 +00:00
Zbigniew Bodek
e0b4b3a74f Remove not working and deprecated PJ4Bv6 support
Sheeva PJ4Bv6 - based chips were only prototypes for V7 class Armada
SoC family. Current in-tree support for PJ4Bv6 will not work and also
there should be no platforms in active use that would incorporate that
CPU revision.
2013-10-28 21:39:54 +00:00
Ruslan Bukin
03a1c6d1f9 Add CPU ID for ARM Cortex A5.
Approved by:	cognet (mentor)
2013-10-16 15:20:27 +00:00
Ganbold Tsagaankhuu
dd5c5e7147 Add identification for Cortex-A7 (R0) cores.
Reviewed by: cognet@
2013-08-01 10:06:19 +00:00
Aleksandr Rybalko
57ae6edf31 Add identification for Cortex-A15 (R0) cores.
Submitted by:	Ruslan Bukin <br@bsdpad.com>
2013-06-28 22:31:17 +00:00
Grzegorz Bernacki
b8b08befd0 Switch to AP[2:1] access permissions model. Store "referenced"
bit in PTE.

Enable Access Flag in CPU control. With AF enabled each valid mapping
needs to have referenced bit in PTE set in order to be able to cache
it in the TLB.

AP[0] bit is to be used as reference flag.
All access permissions are encoded by AP[2:1] wherein AP[1] is in fact
"user enable" and AP[2](APX) is "write disable".

All mappings are always set to be valid. Reference emulation is performed
by setting/clearing reference flag in PTE.

md.pvh_attrs are no longer necessary however pv_flags are still being used
for now.

Marking vm_page as "dirty" or "referenced" is being performed on:
- page or flag fault servicing in pmap_fault_fixup(), basing on the fault
  type
- vm_fault servicing in pmap_enter() according to the desired protections
  and faulty access type
Redundant page marking has been removed as on ARM we know exactly when the
particular page is referenced or is going to be written.

Submitted by:	Zbigniew Bodek <zbb@semihalf.com>
Sponsored by:	The FreeBSD Foundation, Semihalf
2013-05-23 12:07:41 +00:00
Wojciech A. Koszek
735c7fe55e Add Xilinx Zynq ARM/FPGA SoC support to FreeBSD/arm port.
Submitted by:	Thomas Skibo <ThomasSkibo (at) sbcglobal.net>
Tested by:	wkoszek (ZedBoard)
Reviewed by:	wkoszek, freebsd-arm@ (no objections raised)
2013-04-27 23:07:49 +00:00
Oleksandr Tymoshenko
c5f8f8946c Replace generic ARM11 option with more specific
support for ARM1136 and ARM1176

Submitted by:	Daisuke Aoyama <aoyama at peach.ne.jp>
Obtained from:	NetBSD
2012-12-20 04:32:02 +00:00
Grzegorz Bernacki
f3d01034bc Support identification of new PJ4B cores.
Obtained from:	Semihalf
2012-09-14 09:38:54 +00:00
Oleksandr Tymoshenko
cf1a573f04 Merging projects/armv6, part 1
Cummulative patch of changes that are not vendor-specific:
	- ARMv6 and ARMv7 architecture support
	- ARM SMP support
	- VFP/Neon support
	- ARM Generic Interrupt Controller driver
	- Simplification of startup code for all platforms
2012-08-15 03:03:03 +00:00
Warner Losh
ee5cac8ab0 trim trailing whitespace 2012-06-13 05:02:51 +00:00
Andrew Turner
0b898a9ef1 Replace the C implementation of __aeabi_read_tp with an assembly version.
This ensures we follow the ABI by preserving registers r1-r3.

Reviewed by:	jmallett, imp
2012-04-16 09:38:20 +00:00
Stanislav Sedov
b30d62be27 - Revert part of r234005, which I did not intend to commit.
Sorry! :(
2012-04-07 23:51:16 +00:00
Stanislav Sedov
47db1ea0bf - Add kernel config file for QEMU-emulated gumstix board. 2012-04-07 23:48:51 +00:00
Kevin Lo
dbb0e359a7 Correct both FA526/FA626TE cpu ids since the cpu id is always
masked with 0xfffffff0
2010-02-20 14:52:07 +00:00
Kevin Lo
4e92112d57 Correct cpu id for FA526.
While I'm here, add cpu id for FA626TE.
2010-02-14 05:02:08 +00:00
Sam Leffler
b74f293f33 add IXP465 and generic IXP425 definition 2008-12-23 04:46:13 +00:00
Sam Leffler
d212022417 Merge WIP from p4:
o recognize ixp435 cpu
o change memory layout for for ixp4xx to not assume memory is aliases
  to 0x10000000 (Cambria/ixp435 memory starts at zero)
o handle 64 irqs for ixp435
o dual EHCI USB 2.0 controller integral to ixp435
o overhaul NPE code for ixp435 and better MAC+MII naming
o updated NPE firmware (including NPE-A image for ixp435/ixp465)
o Gateworks Cambria board support:
  - IDE compact flash
  - MCU
  - front panel LED on i2c bus
  - Octal LED latch

Sanity-tested with NFS-root on Avila and Cambria boards.  Requires
pending boot2 mods for CF-boot on Cambria.
2008-12-13 01:21:37 +00:00
Rafal Jaworowski
ba6faad63c Introduce low-level support for new Marvell core CPUs: 88FR131, 88FR571.
They are compliant with ARMv5TE and integrated on 88F6281 (Kirkwood) and
MV78100 (Discovery) system-on-chip families.

Obtained from:	Marvell, Semihalf
2008-10-13 18:16:54 +00:00
Warner Losh
dfb7d4cdef Merge definitions for ARM9E, ARM10 and ARM11 processors from p4 (which
got them from NetBSD).
2007-10-18 05:06:58 +00:00
Olivier Houchard
5f78cb4a35 XScale core 3 definitions.
Approved by:	re (blanket)
2007-07-27 14:54:27 +00:00
Olivier Houchard
676b1fbdbf Identify the xscale 81342. 2006-11-07 22:36:57 +00:00
Olivier Houchard
11d1528ce0 Finally bring it support for the i80219 XScale processor.
Submitted by:	Max M. Boyarov <m.boyarov bsd by>
2006-08-24 23:51:28 +00:00
Olivier Houchard
f9126cfb8f Add an alternate ID for the arm920t (the real solution is to have
per-cpu class masks, but oh well).
2005-11-21 19:06:25 +00:00
Warner Losh
d8315c79d9 Start all license statements with /*- 2005-01-05 21:58:49 +00:00
Olivier Houchard
6fc729af63 Import FreeBSD/arm kernel bits.
It only supports sa1110 (on simics) right now, but xscale support should come
soon.
Some of the initial work has been provided by :
Stephane Potvin <sepotvin at videotron.ca>
Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00