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19 Commits

Author SHA1 Message Date
John Baldwin
e0636bc0ca Remove use of explicit bus space tags and handles and use methods that 
operate on resource objects instead.

MFC after:	1 week
 2012-01-05 16:27:32 +00:00
Jack F Vogel
73e3bb6563 Chipset support for the new Intel Panther Point PCH, thanks 
to Seth Heasley for preparing the changes.
 2011-05-11 20:31:27 +00:00
Attilio Rao
bb83df766c Don't assume that SMI are enabled when attaching ichwd and then do 
correct unwind based on former state.

Sponsored by:	Sandvine Incorporated
Reviewed by:	des
MFC after:	1 week
 2011-04-25 14:10:33 +00:00
Attilio Rao
d0827a169b Add some more bit definitions: 
- TCO_MESSAGEx: TCO specific regs providing the ability to monitor BIOS
  bootup activity.
- TCO_NEWCENTURY: reporting RTC year roll over.
- TCO_NMI2SMI_EN, TCO_NMI_NOW: controlling SMIs conversion to NMIs and
  NMI trigger.
- SMI_GBL_EN: Enabling SMI delivery for all the northbridge controller.

MFC after:	10 days
 2011-04-21 14:39:33 +00:00
Jack F Vogel
bf0477b215 Support for the new Patsburg PCH chipset: 
- SMBus Controller
     - SATA Controller
     - HD Audio Controller
     - Watchdog Controller

Thanks to Seth Heasley (seth.heasley@intel.com) for providing us code.

MFC after 3 days
 2011-02-01 01:05:11 +00:00
Jack F Vogel
d5267ede37 Support for the new DH89xxCC PCH chipset including: 
- SATA controller
      - Watchdog timer
      - SMBus controller
 2011-01-31 18:41:52 +00:00
Attilio Rao
cb1f5a37e9 Use convenience macro for minimum and maximum value capping when 
re-arming the watchdog timeout.

Sponsored by:	Sandvine Incorporated
Submitted by:	Mark Johnston <mjohnston at sandvine dot com>
Reviewed by:	des
MFC after:	10 days
 2010-12-08 15:32:54 +00:00
Jack F Vogel
6d23f8741b Add Intel Cougar Point PCH LPC Controller Device IDs 
for watchdog support. Also add additional Intel Ibex
Peak (5 Series/3400 Series) PCH IDs.

MFC after a week
 2010-08-28 00:09:46 +00:00
Remko Lodder
b6a18bc939 Add support for the NM10 chipset. 
PR:		kern/143118
Submitted by:	Koshin sumitani <ksumitani at mui dot biglobe dot ne dot jp>
Approved by:	imp (mentor, implicit)
MFC after:	3 days
 2010-01-24 10:50:20 +00:00
Ed Maste
b8c05be0c1 Add H55 ID from Mike Tancsa, with minor rewording from avg@. 
PR:		kern/143068
Submitted by:	Mike Tancsa (Sentex)
MFC after:	1 week
 2010-01-22 16:05:10 +00:00
John Baldwin
94bf3b9f69 Add more PCI IDs including those for ICH10. 
PR:		kern/126736
Submitted by:	Olivier Smedts  olivier of gid0 org
MFC after:	1 week
 2008-08-25 15:23:54 +00:00
Dag-Erling Smørgrav
909a07a8cf Add support for ICH8M. 
PR:		kern/119351
Submitted by:	Takeharu KATO <takeharu1219@ybb.ne.jp>
MFC after:	1 week
 2008-01-07 09:46:39 +00:00
Dag-Erling Smørgrav
89dbcee8ce Add device IDs for the ICH9 family. 
PR:		i386/119126
Submitted by:	Dan Lukes <dan@obluda.cz>
MFC after:	1 week
 2007-12-31 11:44:01 +00:00
Dag-Erling Smørgrav
abb75f864a Tabify. 2007-12-31 11:42:31 +00:00
Jack F Vogel
b8b1729d3c Add PCI device support for Intel S7000FC4UR in usb and ichwd, systems 
will not install without the usb changes in the install kernel, so I
would like to MFC this in time for 7.0 RC

MFC: 3 days
 2007-11-15 23:59:36 +00:00
Dag-Erling Smørgrav
438dafbbcf Update to support ICH[678] chipsets (based on a patch by Takeharu KATO) 
Fix a resource allocation bug (explained by jhb on -acpi)
Thanks for Mike Tancsa for testing and helping track down the bug.

Approved by:	re (kensmith)
MFC after:	3 weeks
 2007-08-13 18:52:37 +00:00
Doug Ambrisko
c094bde40d Re-work the bus attachment somewhat. Make the rids unique for 
the SMI/TCO address space.  Switch the bus space I/O to the
one specific for either the SMI or TCO space.  Re-calibrate
the tick.  Add some more device id's, 82801FBR submitted by des.
This makes it work on the platforms I've tested with.

Go ahead by:	des
 2006-02-17 18:46:18 +00:00
Warner Losh
098ca2bda9 Start each of the license/copyright comments with /*-, minor shuffle of lines 2005-01-06 01:43:34 +00:00
Dag-Erling Smørgrav
cae8da6164 Add a driver for the watchdog timer function present on the LPC interface 
bridge in Intel ICH-series chipsets.

The original implementation was by W. Daryl Hawkins of Texas A&M, but I
have made substantial modifications.
 2004-05-11 18:21:38 +00:00