in geom_disk.c.
As a side effect this makes a lot of #include <sys/devicestat.h>
lines not needed and some biofinish() calls can be reduced to
biodone() again.
Include read streaming in the PPR flags we display in diagnostics.
In ahd_reset(), set the known mode after our initial pause prior to
setting the mode. We can't just set the mode directly because the
current mode, after the pause, is most likely unknown and setting the
mode when the saved mode is unknown will trigger an assertion in
the mode debug code.
Complete an audit for SCB RAM reads. These reads must be performed
via the special ahd_in?_scbram() methods so we can perform a
Rev A. PCI-X workaround.
Remove a superfluous mode save operation that was performed just
prior to a call to ahd_clear_critical_section(). The saved mode
was never restored and wouldn't have been valid anyway since the
mode could change while single stepping out of a critical section.
aic79xx.h:
Add new BUG definition AHD_PCIX_SCBRAM_RD_BUG.
aic79xx_inline.h:
Update ahd_inb_scbram routine to check for AHD_PCIX_SCBRAM_RD_BUG
and only apply the workaround if this bug is active. The old code
applied the workaround in all cases.
aic79xx_pci.c:
Set AHD_PCIX_SCBRAM_RD_BUG for the A4.
Remove an attempted saved_modes call in ahd_pci_test_register_access().
Saving the modes can only occur when we are paused, but the call was
happening before the chip was known to be paused. Restoring the
modes doesn't make sense either since the code makes no assumptions
about the state of the sequencer until the first time the mode is set
by the driver. This happens after the registers are successfully
mapped.
Submitted by Hiroyuki Aizu <eyes@navi.org>
(refer to [FreeBSD-users-jp 65061])
Tested by Hiroharu Tamaru <tamaru@myn.rcast.u-tokyo.ac.jp>
(refer to [bsd-usb:689])
drain routines are done by swi_net, which allows for better queue control
at some future point. Packets may also be directly dispatched to a netisr
instead of queued, this may be of interest at some installations, but
currently defaults to off.
Reviewed by: hsu, silby, jayanth, sam
Sponsored by: DARPA, NAI Labs
branches:
Initialize struct cdevsw using C99 sparse initializtion and remove
all initializations to default values.
This patch is automatically generated and has been tested by compiling
LINT with all the fields in struct cdevsw in reverse order on alpha,
sparc64 and i386.
Approved by: re(scottl)
This should fix some problem of SBP2 device probing.
Prior to rev 1.41, we keep writing the register while bus reset phase.
But in rev 1.41, we ignore successive bus reset events and some chips seem to
clear the register after we write to it.
Tested by: Michael Reifenberger <root@nihil.reifenberger.com>
Clear the LQICRC_NLQ status should it pop up after we have
already handled the SCSIPERR. During some streaming operations
this status can be delayed until the stream ends. Without this
change, the driver would complain about a "Missing case in
ahd_handle_scsiint".
In the LQOBUSFREE handler...
Don't return the LQOMGR back to the idle state until after
we have cleaned up ENSELO and any status related to this
selection. The last thing we need is the LQO manager starting
another select-out before we have updated the execution queue.
It is not clear whether the LQOMGR would, or would not
start a new selection early.
Make sure ENSELO is off prior to clearing SELDO by flushing
device writes.
Move assignment of the next target SCB pointer inside of
an if to make the code clearer. The effect is the same.
Dump card state in both "Unexpected PKT busfree" paths.
In ahd_reset(), set the chip to SCSI mode before reading SXFRCTL1.
That register only exists in the SCSI mode. Also set the mode
explicitly to the SCSI mode after chip reset due to paranoia.
Re-arrange code so that SXFRCTL1 is restored as quickly after the
chip reset as possible.
S/G structurs must be 8byte aligned. Make this official by saying
so in our DMA tag.
Disable CIO bus stretch on MDFFSTAT if SHVALID is about to come
true. This can cause a CIO bus lockup if a PCI or PCI-X error
occurs while the stretch is occurring - the host cannot service
the PCI-X error since the CIO bus is locked out and SHVALID will
never resolve. The stretch was added in the Rev B to simplify the
wait for SHVALID to resolve, but the code to do this in the open
source sequencer is so simple it was never removed.
Consistently use MAX_OFFSET for the user max syncrate set from
non-volatile storage. This ensures that the offset does not
conflict with AH?_OFFSET_UNKNOWN.
Have ahd_pause_and_flushwork set the mode to ensure that it has
access to the registers it checks. Also modify the checking of
intstat so that the check against 0xFF can actually succeed if
the INT_PEND mask is something other than 0xFF. Although there
are no cardbus U320 controllers, this check may be needed to
recover from a hot-plug PCI removal that occurs without informing
the driver.
Fix a typo. sg_prefetch_cnt -> sg_prefetch_align. This fixes
an infinite loop at card initialization if the cacheline size is 0.
aic79xx.h:
Add AHD_EARLY_REQ_BUG bug flag.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
Change AH?_OFFSET_UNKNOWN to 0xFF. This is a value that the
curr->offset can never be, unlike '0' which we previously used.
This fixes code that only checks for a non-zero offset to
determine if a sync negotiation is required since it will fire
in the unknown case even if the goal is async.
aic79xx.reg:
Add comments for LQISTAT bits indicating their names in the 7902
data book. We use slightly different and more descriptive names
in the firmware.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
aic79xx.seq:
Update comments regarding rundown of the GSFIFO to reflect reality.
Fix spelling errors.
Since we use an 8byte address and 1 byte length, shorten the size
of a block move for the legacy DMA'ed CDB case from 11 to 9 bytes.
Remove code that, assuming the abort pending feature worked, would
set MK_MESSAGE in the SCB's control byte on completion to catch
invalid reselections. Since we don't see interrupts for completed
selections, this status update could occur prior to us noticing the
SELDO. The "select-out" queue logic will get confused by the
MK_MESSAGE bit being set as this is used to catch packatized
connections where we select-out with ATN. Since the abort pending
feature doesn't work on any released controllers yet, this code was
never executed.
Add support for the AHD_EARLY_REQ_BUG. Don't ignore persistent REQ
assertions just because they were asserted within the bus settle delay
window. This allows us to tolerate devices like the GEM318 that
violate the SCSI spec.
Remove unintentional settnig of SG_CACHE_AVAIL. Writing this bit
should have no effect, but who knows...
On the Rev A, we must wait for HDMAENACK before loading additional
segments to avoid clobbering the address of the first segment in
the S/G FIFO. This resolves data-corruption issues with certain
IBM (now Hitachi) and Fujitsu U320 drives.
Rearrange calc_residual to avoid an extra jmp instruction.
On RevA Silicon, if the target returns us to data-out after we
have already trained for data-out, it is possible for us to
transition the free running clock to data-valid before the required
100ns P1 setup time (8 P1 assertions in fast-160 mode). This will
only happen if this L-Q is a continuation of a data transfer for
which we have already prefetched data into our FIFO (LQ/Data
followed by LQ/Data for the same write transaction). This can
cause some target implementations to miss the first few data
transfers on the bus. We detect this situation by noticing that
this is the first data transfer after an LQ (LQIWORKONLQ true),
that the data transfer is a continuation of a transfer already
setup in our FIFO (SAVEPTRS interrupt), and that the transaction
is a write (DIRECTION set in DFCNTRL). The delay is performed by
disabling SCSIEN until we see the first REQ from the target.
Only compile in snapshot savepointers handler for RevA silicon
where it is enabled.
Handle the cfg4icmd packetized interrupt. We just need to load
the address and count, start the DMA, and CLRCHN once the transfer
is complete.
Fix an oversight in the overrun handler for packetized status
operations. We need to wait for either CTXTDONE or an overrun
when checking for an overrun. The previous code did not wait
and thus could decide that no overrun had occurred even though
an overrun will occur on the next data-valid req. Add some
comment to this section for clarity.
Use LAST_SEG_DONE instead of LASTSDONE for testing transfer
completion in the packetized status case. LASTSDONE may come up
more quickly since it only records completion on the SCSI side,
but since LAST_SEG_DONE is used everywhere else (and needs to be),
this is less confusing.
Add a missing invalidation of the longjmp address in the non-pack
handler. This code needs additional review.
aic79xx_inline.h:
Fix spelling error.
aic79xx_osm.c:
Set the cdb length for CDBs dma'ed from host memory.
Add a comment indicating that, should CAM start supporting cdbs
larger than 16bytes, the driver could store the CDB in the status
buffer.
aic79xx_pci.c:
Add a table entry for the 39320A.
Added a missing comma to an error string table.
Fix spelling errors.
