Commit Graph

8 Commits

Author SHA1 Message Date
Adrian Chadd
ef19855701 Oops - fix typo. 2015-07-03 07:00:24 +00:00
Adrian Chadd
3facd56c71 Add register defines for the QCA955x DDR flush and GPIO control. 2015-07-03 03:32:54 +00:00
Adrian Chadd
358811c4e3 add QCA955x PCIe configuration registers.
These are /not/ absolute addresses, as the QCA955x SoC has 2 PCIe RC's
(and 1 PCIe EP.)
2015-03-21 06:00:46 +00:00
Adrian Chadd
4f1cbb2fdc Add DDR flush registers for QCA955x. 2015-03-04 03:51:54 +00:00
Adrian Chadd
5c8bc6bba2 Add Ethernet PLL values for the QCA955x.
These are the same as the AR934x.

Obtained from:	Linux openwrt
2015-03-01 06:54:59 +00:00
Adrian Chadd
b69448850b Make QCA955X_GMAC_REG_ETH_CFG defined like most other registers like this. 2015-03-01 06:52:23 +00:00
Adrian Chadd
e090d1f591 Add an APB base/size for the QCA955X for an upcoming QCA955x specific
APB mux.

It's larger than the AR71xx because it needs to replace the nexus
for some devices (notably wifi) and the wifi driver (if_ath_ahb.c)
reads the SPI data directly at early boot whilst it's memory mapped
in.

I'm eventually going to rip it out and replace it with a firmware
interface similar to what exists for the if_ath_pci.c path -
something early on (likely something new that I'll write) will
suck in the calibration data into a firmware API blob and that'll
be accessed from if_ath_ahb.c.

But, one thing at a time.

Tested:

* QCA955x SoC, AP135 development board
2015-01-06 07:37:33 +00:00
Adrian Chadd
55b32e75df Add QCA955x series register definitions.
There's likely a bunch of register offsets that I have to add the
register window base to before I use them.

Done at:	Hackathon
Obtained from:	Linux OpenWRT
2015-01-05 01:44:23 +00:00