Commit Graph

15 Commits

Author SHA1 Message Date
Adrian Chadd
ff7824ff52 Add in a write barrier after each if_arge write.
Without correct barriers, this code just plain doesn't work on the
mips74k cores (specifically the AR9344.)

In particular, the MDIO register accesses need this barriering or MII bus
access results in out-of-order garbage.

Tested:

* AR9344 (mips74k)
* AR9331 (mips24k)
2013-10-16 02:46:00 +00:00
Adrian Chadd
337ef3cad0 Implement PLL configuration override support, similar to what openwrt
implements.
2012-05-02 07:43:11 +00:00
Adrian Chadd
f014aaebdf Allow the MII mode to be overridden via 'hint.arge.X.miimode'.
It takes a number at the moment, rather than a string.

Some of the Linux board configurations specify the MII mode explicitly.
2012-05-02 06:18:12 +00:00
Adrian Chadd
72b9c70e36 Break out the arge MDIO bus code into an optional argemdio device.
This is only done if the ARGE_MDIO option is included.

* Shuffle the arge MDIO bus into a separate device, that needs to be
  probed early (use hint.argemdio.X.order=0)
* hint.arge.X.mdio now specifies which miiproxy to rendezvous with.
* Call MAC/MDIO bus init during MDIO attach, not arge attach.

This is done regardless:

* Shift the arge MAC and MDIO bus reset code into separate functions
  and call it early during MDIO bus attach.  It's required for
  correct MDIO bus IO to occur on AR71xx/AR91xx devices.

* Remove the AR71xx/AR91xx centric assumption that there's only one
  MDIO bus.  The initial code mapped miibus0(arge0) and miibus1(arge1)
  MII register operations to the MII0 (arge0) register space.  The
  AR724x (and later, upcoming chipsets) have two MDIO busses and
  the second is very much in use.

TODO:

* since the multiphy behaviour has changed (where now a phymask of >1
  PHY will still be enumerated), multiphy setups may be quite wrong.
  I'll go and fix these so they still have a chance of working, at least.
  until the switch PHY support appears in -HEAD.

Submitted by:	Stefan Bethke <stb@lassitu.de>
2012-05-01 06:18:30 +00:00
Adrian Chadd
85df7b525a * Add some more debugging to if_arge
* Make doubly sure that IFF_DRV_OACTIVE is set if the hardware TX queue is full
2011-04-05 06:33:35 +00:00
Adrian Chadd
85a5701186 Fix the TX underrun status reset; remove a now unused variable.
Submitted by: Luiz Otavio O Souza
2011-03-13 08:34:14 +00:00
Adrian Chadd
813b73a5a9 Migrate if_arge to use the PLL cpuops.
This has been lightly tested on the AR7161 and AR9132.
2010-08-19 16:29:08 +00:00
Adrian Chadd
5b877d30b5 Remove the now-unused DDR flush register value. 2010-08-19 02:10:05 +00:00
Adrian Chadd
ff97a64735 Add TX-path aligned/unaligned stats for if_arge. 2010-07-08 15:20:57 +00:00
Adrian Chadd
d06458f7f7 Introduce a sysctl block for if_arge and, for now, a blank debug sysctl
placeholder for later.

Add in a missing FreeBSD ID string.
2010-07-08 14:34:15 +00:00
Oleksandr Tymoshenko
2b8344b8fa - Handle multiphy MAC case: create interface with
fixed-state media with parameters set via hints
    and configure MAC accordingly to these parameters.
    All the underlying PHY magic is done by boot manager
    on startup. At the moment there is no proper way
    to make active and control all PHYs simultaneously
    from one MII bus and there is no way to associate
    incoming/outgoing packet with specific PHY.
2009-11-12 21:27:58 +00:00
Oleksandr Tymoshenko
bec244c750 - Access to all 5 PHYs goes through registers in MAC0 memory
space, rewrite miibus accessors respectively
2009-11-08 07:26:02 +00:00
Oleksandr Tymoshenko
6450bdc708 - Fix initialization of PLL registers (different shifts for
arge0/arge1)
- Use base MAC address to generate MACs for arge1 and above
2009-11-06 06:50:45 +00:00
Oleksandr Tymoshenko
a0d684a583 - Remove noisy "Implement me" stubs
- Handle SIOCSIFFLAGS ioctl
2009-11-04 23:33:36 +00:00
Oleksandr Tymoshenko
fd7391fc0c - Revert changes accidentally killed by merge operation 2009-04-14 22:53:22 +00:00