/* * from: vector.s, 386BSD 0.1 unknown origin * $Id: apic_vector.s,v 1.3 1997/07/06 23:29:00 smp Exp smp $ */ #include /** TEST_CPUSTOP */ /* convert an absolute IRQ# into a bitmask */ #define IRQ_BIT(irq_num) (1 << (irq_num)) /* make an index into the IO APIC from the IRQ# */ #define REDTBL_IDX(irq_num) (0x10 + ((irq_num) * 2)) /* * 'lazy masking' code suggested by Bruce Evans */ #define MAYBE_MASK_IRQ(irq_num) \ testl $IRQ_BIT(irq_num),iactive ; /* lazy masking */ \ je 1f ; /* NOT currently active */ \ orl $IRQ_BIT(irq_num),_imen ; /* set the mask bit */ \ movl _ioapic,%ecx ; /* ioapic[0]addr */ \ movl $REDTBL_IDX(irq_num),(%ecx) ; /* write the index */ \ movl IOAPIC_WINDOW(%ecx),%eax ; /* current value */ \ orl $IOART_INTMASK,%eax ; /* set the mask */ \ movl %eax,IOAPIC_WINDOW(%ecx) ; /* new value */ \ movl $lapic_eoi, %eax ; \ movl $0, (%eax) ; \ orl $IRQ_BIT(irq_num), _ipending ; \ REL_MPLOCK ; /* SMP release global lock */ \ popl %es ; \ popl %ds ; \ popal ; \ addl $4+4,%esp ; \ iret ; \ ; \ ALIGN_TEXT ; \ 1: ; \ orl $IRQ_BIT(irq_num),iactive #define MAYBE_UNMASK_IRQ(irq_num) \ cli ; /* must unmask _imen and icu atomically */ \ andl $~IRQ_BIT(irq_num),iactive ; \ testl $IRQ_BIT(irq_num),_imen ; \ je 2f ; \ andl $~IRQ_BIT(irq_num),_imen ; /* clear mask bit */ \ movl _ioapic,%ecx ; /* ioapic[0]addr */ \ movl $REDTBL_IDX(irq_num),(%ecx) ; /* write the index */ \ movl IOAPIC_WINDOW(%ecx),%eax ; /* current value */ \ andl $~IOART_INTMASK,%eax ; /* clear the mask */ \ movl %eax,IOAPIC_WINDOW(%ecx) ; /* new value */ \ 2: ; \ sti ; /* XXX _doreti repeats the cli/sti */ /* * Macros for interrupt interrupt entry, call to handler, and exit. */ #define FAST_INTR(irq_num, vec_name) \ .text ; \ SUPERALIGN_TEXT ; \ IDTVEC(vec_name) ; \ pushl %eax ; /* save only call-used registers */ \ pushl %ecx ; \ pushl %edx ; \ pushl %ds ; \ MAYBE_PUSHL_ES ; \ movl $KDSEL,%eax ; \ movl %ax,%ds ; \ MAYBE_MOVW_AX_ES ; \ FAKE_MCOUNT((4+ACTUALLY_PUSHED)*4(%esp)) ; \ GET_MPLOCK ; /* SMP Spin lock */ \ pushl _intr_unit + (irq_num) * 4 ; \ call *_intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \ movl $lapic_eoi, %eax ; \ movl $0, (%eax) ; \ addl $4,%esp ; \ incl _cnt+V_INTR ; /* book-keeping can wait */ \ movl _intr_countp + (irq_num) * 4,%eax ; \ incl (%eax) ; \ movl _cpl,%eax ; /* unmasking pending HWIs or SWIs? */ \ notl %eax ; \ andl _ipending,%eax ; \ jne 2f ; /* yes, maybe handle them */ \ 1: ; \ MEXITCOUNT ; \ REL_MPLOCK ; /* SMP release global lock */ \ MAYBE_POPL_ES ; \ popl %ds ; \ popl %edx ; \ popl %ecx ; \ popl %eax ; \ iret ; \ ; \ ALIGN_TEXT ; \ 2: ; \ cmpb $3,_intr_nesting_level ; /* enough stack? */ \ jae 1b ; /* no, return */ \ movl _cpl,%eax ; \ /* XXX next line is probably unnecessary now. */ \ movl $HWI_MASK|SWI_MASK,_cpl ; /* limit nesting ... */ \ incb _intr_nesting_level ; /* ... really limit it ... */ \ sti ; /* to do this as early as possible */ \ MAYBE_POPL_ES ; /* discard most of thin frame ... */ \ popl %ecx ; /* ... original %ds ... */ \ popl %edx ; \ xchgl %eax,4(%esp) ; /* orig %eax; save cpl */ \ pushal ; /* build fat frame (grrr) ... */ \ pushl %ecx ; /* ... actually %ds ... */ \ pushl %es ; \ movl $KDSEL,%eax ; \ movl %ax,%es ; \ movl (2+8+0)*4(%esp),%ecx ; /* %ecx from thin frame ... */ \ movl %ecx,(2+6)*4(%esp) ; /* ... to fat frame ... */ \ movl (2+8+1)*4(%esp),%eax ; /* ... cpl from thin frame */ \ pushl %eax ; \ subl $4,%esp ; /* junk for unit number */ \ MEXITCOUNT ; \ jmp _doreti #define INTR(irq_num, vec_name) \ .text ; \ SUPERALIGN_TEXT ; \ IDTVEC(vec_name) ; \ pushl $0 ; /* dummy error code */ \ pushl $0 ; /* dummy trap type */ \ pushal ; \ pushl %ds ; /* save data and extra segments ... */ \ pushl %es ; \ movl $KDSEL,%eax ; /* ... and reload with kernel's ... */ \ movl %ax,%ds ; /* ... early for obsolete reasons */ \ movl %ax,%es ; \ GET_MPLOCK ; /* SMP Spin lock */ \ MAYBE_MASK_IRQ(irq_num) ; \ movl $lapic_eoi, %eax ; \ movl $0, (%eax) ; \ movl _cpl,%eax ; \ testl $IRQ_BIT(irq_num), %eax ; \ jne 3f ; \ incb _intr_nesting_level ; \ __CONCAT(Xresume,irq_num): ; \ FAKE_MCOUNT(12*4(%esp)) ; /* XXX late to avoid dbl cnt */ \ incl _cnt+V_INTR ; /* tally interrupts */ \ movl _intr_countp + (irq_num) * 4,%eax ; \ incl (%eax) ; \ movl _cpl,%eax ; \ pushl %eax ; \ pushl _intr_unit + (irq_num) * 4 ; \ orl _intr_mask + (irq_num) * 4,%eax ; \ movl %eax,_cpl ; \ sti ; \ call *_intr_handler + (irq_num) * 4 ; \ MAYBE_UNMASK_IRQ(irq_num) ; \ MEXITCOUNT ; \ jmp _doreti ; \ ; \ ALIGN_TEXT ; \ 3: ; \ /* XXX skip mcounting here to avoid double count */ \ orl $IRQ_BIT(irq_num), _ipending ; \ REL_MPLOCK ; /* SMP release global lock */ \ popl %es ; \ popl %ds ; \ popal ; \ addl $4+4,%esp ; \ iret /* * Handle TLB shootdowns. */ .text SUPERALIGN_TEXT .globl _Xinvltlb _Xinvltlb: pushl %eax #ifdef COUNT_XINVLTLB_HITS ss movl _cpuid, %eax ss incl _xhits(,%eax,4) #endif /* COUNT_XINVLTLB_HITS */ movl %cr3, %eax /* invalidate the TLB */ movl %eax, %cr3 movl $lapic_eoi, %eax ss /* stack segment, avoid %ds load */ movl $0, (%eax) /* End Of Interrupt to APIC */ popl %eax iret /* * Handle "spurious INTerrupts". * Notes: * This is different than the "spurious INTerrupt" generated by an * 8259 PIC for missing INTs. See the APIC documentation for details. * This routine should NOT do an 'EOI' cycle. */ .text SUPERALIGN_TEXT .globl _Xspuriousint _Xspuriousint: pushl %eax pushl %ds /* save current data segment */ movl $KDSEL, %eax movl %ax, %ds /* use KERNEL data segment */ #if 1 ASMPOSTCODE_HI(0xc0) #endif #ifdef COUNT_SPURIOUS_INTS incl _sihits #endif /* No EOI cycle used here */ popl %ds /* restore previous data segment */ popl %eax iret #ifdef TEST_CPUSTOP /* * Executed by a CPU when it receives an Xcpustop IPI from another CPU, * * - Signals its receipt. * - Waits for permission to restart. * - Signals its restart. */ .text SUPERALIGN_TEXT .globl _Xcpustop _Xcpustop: pushl %eax pushl %ds /* save current data segment */ movl $KDSEL, %eax movl %ax, %ds /* use KERNEL data segment */ #if 1 /** XXX still trying to make this !^#$#% thing work... */ movl _cpuid, %eax incl _cshits(,%eax,4) #else /** !^#$#% */ ASMPOSTCODE_HI(0x10) movl _cpuid, %eax /* id */ lock btsl %eax, _stopped_cpus /* stopped_cpus |= (1<