b173edafc7
number of the child bus of a host to PCI bridge by reading from proprietary configuration registers in the host to PCI bridge devices. Approved by: re
78 lines
3.3 KiB
C
78 lines
3.3 KiB
C
/*-
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* Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
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* Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
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* Copyright (c) 2000 BSDi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __PCIB_PRIVATE_H__
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#define __PCIB_PRIVATE_H__
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/*
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* Export portions of generic PCI:PCI bridge support so that it can be
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* used by subclasses.
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*/
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/*
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* Bridge-specific data.
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*/
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struct pcib_softc
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{
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device_t dev;
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u_int16_t command; /* command register */
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u_int8_t secbus; /* secondary bus number */
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u_int8_t subbus; /* subordinate bus number */
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pci_addr_t pmembase; /* base address of prefetchable memory */
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pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
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pci_addr_t membase; /* base address of memory window */
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pci_addr_t memlimit; /* topmost address of memory window */
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u_int32_t iobase; /* base address of port window */
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u_int32_t iolimit; /* topmost address of port window */
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u_int16_t secstat; /* secondary bus status register */
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u_int16_t bridgectl; /* bridge control register */
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u_int8_t seclat; /* secondary bus latency timer */
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};
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typedef u_int32_t pci_read_config_fn(int b, int s, int f, int reg, int width);
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int host_pcib_get_busno(pci_read_config_fn read_config, int bus,
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int slot, int func, u_int8_t *busnum);
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int pcib_attach(device_t dev);
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void pcib_attach_common(device_t dev);
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int pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result);
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int pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value);
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struct resource *pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags);
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int pcib_maxslots(device_t dev);
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u_int32_t pcib_read_config(device_t dev, int b, int s, int f, int reg, int width);
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void pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width);
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extern devclass_t pcib_devclass;
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#endif
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