1003 lines
36 KiB
C
1003 lines
36 KiB
C
/*-
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* BSD LICENSE
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*
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* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _SCU_BIOS_DEFINITIONS_H_
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#define _SCU_BIOS_DEFINITIONS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif // __cplusplus
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/**
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* IMPORTANT NOTE:
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* This file can be used by an SCI Library based driver or
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* stand-alone where the library is excluded. By excluding
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* the SCI Library, inclusion of OS specific header files can
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* be avoided. For example, a BIOS utility probably does not
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* want to be bothered with inclusion of nested OS DDK include
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* files that are not necessary for its function.
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*
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* To exclude the SCI Library, either uncomment the EXCLUDE_SCI_LIBRARY
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* #define statement in environment.h or define the statement as an input
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* to your compiler.
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*/
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#include <dev/isci/environment.h>
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#ifndef EXCLUDE_SCI_LIBRARY
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#include <dev/isci/scil/sci_types.h>
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#include <dev/isci/scil/intel_sas.h>
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#include <dev/isci/scil/sci_controller_constants.h>
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#endif /* EXCLUDE_SCI_LIBRARY */
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// For Intel Storage Controller Unit OEM Block
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#define SCI_OEM_PARAM_SIGNATURE "ISCUOEMB"
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#define SCI_PREBOOT_SOURCE_INIT (0x00)
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#define SCI_PREBOOT_SOURCE_OROM (0x80)
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#define SCI_PREBOOT_SOURCE_EFI (0x81)
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#define SCI_OEM_PARAM_VER_1_0 (0x10)
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#define SCI_OEM_PARAM_VER_1_1 (0x11)
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#define SCI_OEM_PARAM_VER_1_2 (0x12)
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#define SCI_OEM_PARAM_VER_1_3 (0x13)
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// current version
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#define SCI_OEM_PARAM_VER_CUR SCI_OEM_PARAM_VER_1_3
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// port configuration mode
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#define SCI_BIOS_MODE_MPC (0x00)
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#define SCI_BIOS_MODE_APC (0x01)
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#ifndef SCI_MAX_PHYS
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#define SCI_MAX_PHYS (4)
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#endif
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#ifndef SCI_MAX_PORTS
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#define SCI_MAX_PORTS (4)
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#endif
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/**
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* @struct SCI_BIOS_OEM_PARAM_BLOCK_HDR
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*
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* @brief This structure defines the OEM Parameter block header.
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*/
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typedef struct SCI_BIOS_OEM_PARAM_BLOCK_HDR
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{
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/**
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* This field contains the OEM Parameter Block Signature which is
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* used by BIOS and driver software to identify that the memory location
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* contains valid OEM Parameter data. The value must be set to
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* SCI_OEM_PARAM_SIGNATURE which is the string "ISCUOEMB" which
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* stands for Intel Storage Controller Unit OEM Block.
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*/
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U8 signature[8];
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/**
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* This field contains the size in bytes of the complete OEM
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* Parameter Block, both header and payload hdr_length +
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* (num_elements * element_length).
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*/
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U16 total_block_length;
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/**
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* This field contains the size in bytes of the
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* SCI_BIOS_OEM_PARAM_BLOCK_HDR. It also indicates the offset from
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* the beginning of this data structure to where the actual
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* parameter data payload begins.
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*/
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U8 hdr_length;
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/**
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* This field contains the version info defining the structure
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* of the OEM Parameter block.
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*/
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U8 version;
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/**
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* This field contains a value indicating the preboot initialization
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* method (Option ROM or UEFI driver) so that after OS transition,
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* the OS driver can know the preboot method. OEMs who build a single
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* flash image where the preboot method is unknown at manufacturing
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* time should set this field to SCI_PREBOOT_SOURCE_INIT. Then
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* after the block is retrieved into host memory and under preboot
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* driver control, the OROM or UEFI driver can set this field
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* appropriately (SCI_PREBOOT_SOURCE_OROM and SCI_PREBOOT_SOURCE_EFI,
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* respectively).
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*/
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U8 preboot_source;
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/**
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* This field contains the number of parameter descriptor elements
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* (i.e. controller_elements) following this header. The number of
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* elements corresponds to the number of SCU controller units contained
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* in the platform:
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* controller_element[0] = SCU0
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* controller_element[1] = SCU1
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*/
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U8 num_elements;
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/**
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* This field contains the size in bytes of the descriptor element(s)
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* in the block.
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*/
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U16 element_length;
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/**
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* Reserve fields for future use.
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*/
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U8 reserved[8];
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} SCI_BIOS_OEM_PARAM_BLOCK_HDR_T;
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/**
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* @struct SCIC_SDS_OEM_PARAMETERS VER 1.0
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*
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* @brief This structure delineates the various OEM parameters that must
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* be set for the Intel SAS Storage Controller Unit (SCU).
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*/
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typedef struct SCI_BIOS_OEM_PARAM_ELEMENT
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{
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/**
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* Per SCU Controller Data
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*/
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struct
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{
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/**
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* This field indicates the port configuration mode for
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* this controller:
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* Automatic Port Configuration(APC) or
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* Manual Port Configuration (MPC).
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*
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* APC means the Platform OEM expects SCI to configure
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* SAS Ports automatically according to the discovered SAS
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* Address pairs of the endpoints, wide and/or narrow.
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*
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* MPC means the Platform OEM manually defines wide or narrow
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* connectors by apriori assigning PHYs to SAS Ports.
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*
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* By default, the mode type is APC
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* in APC mode, if ANY of the phy mask is non-zero,
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* SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned
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* from scic_oem_parameters_set AND the default oem
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* configuration will be applied
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* in MPC mode, if ALL of the phy masks are zero,
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* SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned
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* from scic_oem_parameters_set AND the default oem
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* configuration will be applied
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*/
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U8 mode_type;
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/**
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* This field specifies the maximum number of direct attached
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* devices the OEM will allow to have powered up simultaneously
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* on this controller. This allows the OEM to avoid exceeding
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* power supply limits for this platform. A value of zero
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* indicates there are no restrictions.
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*/
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U8 max_number_concurrent_device_spin_up;
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/**
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* This field indicates OEM's desired default
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* Spread Spectrum Clocking (SSC) setting for Tx:
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* enabled = 1
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* disabled = 0
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*/
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U8 do_enable_ssc;
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U8 reserved;
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} controller;
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/**
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* Per SAS Port data.
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*/
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struct
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{
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/**
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* This field specifies the phys to be contained inside a port.
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* The bit position in the mask specifies the index of the phy
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* to be contained in the port. Multiple bits (i.e. phys)
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* can be contained in a single port:
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* Bit 0 = This controller's PHY index 0 (0x01)
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* Bit 1 = This controller's PHY index 1 (0x02)
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* Bit 2 = This controller's PHY index 2 (0x04)
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* Bit 3 = This controller's PHY index 3 (0x08)
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*
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* Refer to the mode_type field for rules regarding APC and MPC mode.
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* General rule: For APC mode phy_mask = 0
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*/
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U8 phy_mask;
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} ports[SCI_MAX_PORTS]; // Up to 4 Ports per SCU controller unit
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/**
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* Per PHY Parameter data.
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*/
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struct
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{
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/**
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* This field indicates the SAS Address that will be transmitted on
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* this PHY index. The field is defined as a union, however, the
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* OEM should use the U8 array definition when encoding it to ensure
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* correct byte ordering.
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*
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* NOTE: If using APC MODE, along with phy_mask being set to ZERO, the
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* SAS Addresses for all PHYs within a controller group SHALL be the
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* same.
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*/
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union
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{
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/**
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* The array should be stored in little endian order. For example,
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* if the desired SAS Address is 0x50010B90_0003538D, then it
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* should be stored in the following manner:
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* array[0] = 0x90
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* array[1] = 0x0B
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* array[2] = 0x01
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* array[3] = 0x50
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* array[4] = 0x8D
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* array[5] = 0x53
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* array[6] = 0x03
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* array[7] = 0x00
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*/
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U8 array[8];
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/**
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* This is the typedef'd version of the SAS Address used in
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* the SCI Library.
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*/
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SCI_SAS_ADDRESS_T sci_format;
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} sas_address;
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/**
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* These are the per PHY equalization settings associated with the
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* AFE XCVR Tx Amplitude and Equalization Control Register Set
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* (0 thru 3).
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*
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* Operational Note: The following Look-Up-Table registers are engaged
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* by the AFE block after the following:
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* - Software programs the Link Layer AFE Look Up Table Control
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* Registers (AFE_LUTCR).
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* - Software sets AFE XCVR Tx Control Register Tx Equalization
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* Enable bit.
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*/
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/**
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* AFE_TX_AMP_CTRL0. This register is associated with AFE_LUTCR
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* LUTSel=00b. It contains the Tx Equalization settings that will be
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* used if a SATA 1.5Gbs or SATA 3.0Gbs device is direct-attached.
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*/
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U32 afe_tx_amp_control0;
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/**
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* AFE_TX_AMP_CTRL1. This register is associated with AFE_LUTCR
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* LUTSel=01b. It contains the Tx Equalization settings that will
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* be used if a SATA 6.0Gbs device is direct-attached.
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*/
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U32 afe_tx_amp_control1;
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/**
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* AFE_TX_AMP_CTRL2. This register is associated with AFE_LUTCR
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* LUTSel=10b. It contains the Tx Equalization settings that will
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* be used if a SAS 1.5Gbs or SAS 3.0Gbs device is direct-attached.
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*/
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U32 afe_tx_amp_control2;
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/**
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* AFE_TX_AMP_CTRL3. This register is associated with AFE_LUTCR
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* LUTSel=11b. It contains the Tx Equalization settings that will
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* be used if a SAS 6.0Gbs device is direct-attached.
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*/
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U32 afe_tx_amp_control3;
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} phys[SCI_MAX_PHYS]; // 4 PHYs per SCU controller unit
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} SCI_BIOS_OEM_PARAM_ELEMENT_T;
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/**
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* @struct SCIC_SDS_OEM_PARAMETERS VER 1.1
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*
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* @brief This structure delineates the various OEM parameters that must
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* be set for the Intel SAS Storage Controller Unit (SCU).
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*/
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typedef struct SCI_BIOS_OEM_PARAM_ELEMENT_v_1_1
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{
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/**
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* Per SCU Controller Data
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*/
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struct
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{
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/**
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* This field indicates the port configuration mode for
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* this controller:
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* Automatic Port Configuration(APC) or
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* Manual Port Configuration (MPC).
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|
*
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* APC means the Platform OEM expects SCI to configure
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* SAS Ports automatically according to the discovered SAS
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* Address pairs of the endpoints, wide and/or narrow.
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|
*
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* MPC means the Platform OEM manually defines wide or narrow
|
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* connectors by apriori assigning PHYs to SAS Ports.
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*
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* By default, the mode type is APC
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* in APC mode, if ANY of the phy mask is non-zero,
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* SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned
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* from scic_oem_parameters_set AND the default oem
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* configuration will be applied
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* in MPC mode, if ALL of the phy masks are zero,
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* SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned
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* from scic_oem_parameters_set AND the default oem
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* configuration will be applied
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*/
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U8 mode_type;
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/**
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* This field specifies the maximum number of direct attached
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* devices the OEM will allow to have powered up simultaneously
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* on this controller. This allows the OEM to avoid exceeding
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* power supply limits for this platform. A value of zero
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* indicates there are no restrictions.
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*/
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U8 max_number_concurrent_device_spin_up;
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/**
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* This bitfield indicates the OEM's desired default Tx
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* Spread Spectrum Clocking (SSC) settings for SATA and SAS.
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* NOTE: Default SSC Modulation Frequency is 31.5KHz.
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*--------------------------------------------------------------------*/
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/**
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* NOTE: Max spread for SATA is +0 / -5000 PPM.
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* Down-spreading SSC (only method allowed for SATA):
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* SATA SSC Tx Disabled = 0x0
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* SATA SSC Tx at +0 / -1419 PPM Spread = 0x2
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* SATA SSC Tx at +0 / -2129 PPM Spread = 0x3
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* SATA SSC Tx at +0 / -4257 PPM Spread = 0x6
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* SATA SSC Tx at +0 / -4967 PPM Spread = 0x7
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*/
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U8 ssc_sata_tx_spread_level : 4;
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/**
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* SAS SSC Tx Disabled = 0x0
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*
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* NOTE: Max spread for SAS down-spreading +0 / -2300 PPM
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* Down-spreading SSC:
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* SAS SSC Tx at +0 / -1419 PPM Spread = 0x2
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* SAS SSC Tx at +0 / -2129 PPM Spread = 0x3
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*
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* NOTE: Max spread for SAS center-spreading +2300 / -2300 PPM
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* Center-spreading SSC:
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* SAS SSC Tx at +1064 / -1064 PPM Spread = 0x3
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* SAS SSC Tx at +2129 / -2129 PPM Spread = 0x6
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*/
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U8 ssc_sas_tx_spread_level : 3;
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/**
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* NOTE: Refer to the SSC section of the SAS 2.x Specification
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* for proper setting of this field. For standard SAS Initiator
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* SAS PHY operation it should be 0 for Down-spreading.
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* SAS SSC Tx spread type:
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* Down-spreading SSC = 0
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* Center-spreading SSC = 1
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*/
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U8 ssc_sas_tx_type : 1;
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/*--------------------------------------------------------------------*/
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U8 reserved;
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} controller;
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|
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/**
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* Per SAS Port data.
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*/
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struct
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{
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/**
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* This field specifies the phys to be contained inside a port.
|
|
* The bit position in the mask specifies the index of the phy
|
|
* to be contained in the port. Multiple bits (i.e. phys)
|
|
* can be contained in a single port:
|
|
* Bit 0 = This controller's PHY index 0 (0x01)
|
|
* Bit 1 = This controller's PHY index 1 (0x02)
|
|
* Bit 2 = This controller's PHY index 2 (0x04)
|
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* Bit 3 = This controller's PHY index 3 (0x08)
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|
*
|
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* Refer to the mode_type field for rules regarding APC and MPC mode.
|
|
* General rule: For APC mode phy_mask = 0
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*/
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U8 phy_mask;
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} ports[SCI_MAX_PORTS]; // Up to 4 Ports per SCU controller unit
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|
|
|
/**
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|
* Per PHY Parameter data.
|
|
*/
|
|
struct
|
|
{
|
|
/**
|
|
* This field indicates the SAS Address that will be transmitted on
|
|
* this PHY index. The field is defined as a union, however, the
|
|
* OEM should use the U8 array definition when encoding it to ensure
|
|
* correct byte ordering.
|
|
*
|
|
* NOTE: If using APC MODE, along with phy_mask being set to ZERO, the
|
|
* SAS Addresses for all PHYs within a controller group SHALL be the
|
|
* same.
|
|
*/
|
|
union
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|
{
|
|
/**
|
|
* The array should be stored in little endian order. For example,
|
|
* if the desired SAS Address is 0x50010B90_0003538D, then it
|
|
* should be stored in the following manner:
|
|
* array[0] = 0x90
|
|
* array[1] = 0x0B
|
|
* array[2] = 0x01
|
|
* array[3] = 0x50
|
|
* array[4] = 0x8D
|
|
* array[5] = 0x53
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|
* array[6] = 0x03
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|
* array[7] = 0x00
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|
*/
|
|
U8 array[8];
|
|
/**
|
|
* This is the typedef'd version of the SAS Address used in
|
|
* the SCI Library.
|
|
*/
|
|
SCI_SAS_ADDRESS_T sci_format;
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|
|
|
} sas_address;
|
|
|
|
/**
|
|
* These are the per PHY equalization settings associated with the
|
|
* AFE XCVR Tx Amplitude and Equalization Control Register Set
|
|
* (0 thru 3).
|
|
*
|
|
* Operational Note: The following Look-Up-Table registers are engaged
|
|
* by the AFE block after the following:
|
|
* - Software programs the Link Layer AFE Look Up Table Control
|
|
* Registers (AFE_LUTCR).
|
|
* - Software sets AFE XCVR Tx Control Register Tx Equalization
|
|
* Enable bit.
|
|
*/
|
|
/**
|
|
* AFE_TX_AMP_CTRL0. This register is associated with AFE_LUTCR
|
|
* LUTSel=00b. It contains the Tx Equalization settings that will be
|
|
* used if a SATA 1.5Gbs or SATA 3.0Gbs device is direct-attached.
|
|
*/
|
|
U32 afe_tx_amp_control0;
|
|
|
|
/**
|
|
* AFE_TX_AMP_CTRL1. This register is associated with AFE_LUTCR
|
|
* LUTSel=01b. It contains the Tx Equalization settings that will
|
|
* be used if a SATA 6.0Gbs device is direct-attached.
|
|
*/
|
|
U32 afe_tx_amp_control1;
|
|
|
|
/**
|
|
* AFE_TX_AMP_CTRL2. This register is associated with AFE_LUTCR
|
|
* LUTSel=10b. It contains the Tx Equalization settings that will
|
|
* be used if a SAS 1.5Gbs or SAS 3.0Gbs device is direct-attached.
|
|
*/
|
|
U32 afe_tx_amp_control2;
|
|
|
|
/**
|
|
* AFE_TX_AMP_CTRL3. This register is associated with AFE_LUTCR
|
|
* LUTSel=11b. It contains the Tx Equalization settings that will
|
|
* be used if a SAS 6.0Gbs device is direct-attached.
|
|
*/
|
|
U32 afe_tx_amp_control3;
|
|
|
|
} phys[SCI_MAX_PHYS]; // 4 PHYs per SCU controller unit
|
|
|
|
} SCI_BIOS_OEM_PARAM_ELEMENT_v_1_1_T;
|
|
|
|
/**
|
|
* @struct SCIC_SDS_OEM_PARAMETERS VER 1.2
|
|
*
|
|
* @brief This structure delineates the various OEM parameters that must
|
|
* be set for the Intel SAS Storage Controller Unit (SCU).
|
|
*/
|
|
typedef struct SCI_BIOS_OEM_PARAM_ELEMENT_v_1_2
|
|
{
|
|
/**
|
|
* Per SCU Controller Data
|
|
*/
|
|
struct
|
|
{
|
|
/**
|
|
* This field indicates the port configuration mode for
|
|
* this controller:
|
|
* Automatic Port Configuration(APC) or
|
|
* Manual Port Configuration (MPC).
|
|
*
|
|
* APC means the Platform OEM expects SCI to configure
|
|
* SAS Ports automatically according to the discovered SAS
|
|
* Address pairs of the endpoints, wide and/or narrow.
|
|
*
|
|
* MPC means the Platform OEM manually defines wide or narrow
|
|
* connectors by apriori assigning PHYs to SAS Ports.
|
|
*
|
|
* By default, the mode type is APC
|
|
* in APC mode, if ANY of the phy mask is non-zero,
|
|
* SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned
|
|
* from scic_oem_parameters_set AND the default oem
|
|
* configuration will be applied
|
|
* in MPC mode, if ALL of the phy masks are zero,
|
|
* SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned
|
|
* from scic_oem_parameters_set AND the default oem
|
|
* configuration will be applied
|
|
*/
|
|
U8 mode_type;
|
|
|
|
/**
|
|
* This field specifies the maximum number of direct attached
|
|
* devices the OEM will allow to have powered up simultaneously
|
|
* on this controller. This allows the OEM to avoid exceeding
|
|
* power supply limits for this platform. A value of zero
|
|
* indicates there are no restrictions.
|
|
*/
|
|
U8 max_number_concurrent_device_spin_up;
|
|
|
|
/**
|
|
* This bitfield indicates the OEM's desired default Tx
|
|
* Spread Spectrum Clocking (SSC) settings for SATA and SAS.
|
|
* NOTE: Default SSC Modulation Frequency is 31.5KHz.
|
|
*--------------------------------------------------------------------*/
|
|
/**
|
|
* NOTE: Max spread for SATA is +0 / -5000 PPM.
|
|
* Down-spreading SSC (only method allowed for SATA):
|
|
* SATA SSC Tx Disabled = 0x0
|
|
* SATA SSC Tx at +0 / -1419 PPM Spread = 0x2
|
|
* SATA SSC Tx at +0 / -2129 PPM Spread = 0x3
|
|
* SATA SSC Tx at +0 / -4257 PPM Spread = 0x6
|
|
* SATA SSC Tx at +0 / -4967 PPM Spread = 0x7
|
|
*/
|
|
U8 ssc_sata_tx_spread_level : 4;
|
|
|
|
/**
|
|
* SAS SSC Tx Disabled = 0x0
|
|
*
|
|
* NOTE: Max spread for SAS down-spreading +0 / -2300 PPM
|
|
* Down-spreading SSC:
|
|
* SAS SSC Tx at +0 / -1419 PPM Spread = 0x2
|
|
* SAS SSC Tx at +0 / -2129 PPM Spread = 0x3
|
|
*
|
|
* NOTE: Max spread for SAS center-spreading +2300 / -2300 PPM
|
|
* Center-spreading SSC:
|
|
* SAS SSC Tx at +1064 / -1064 PPM Spread = 0x3
|
|
* SAS SSC Tx at +2129 / -2129 PPM Spread = 0x6
|
|
*/
|
|
U8 ssc_sas_tx_spread_level : 3;
|
|
/**
|
|
* NOTE: Refer to the SSC section of the SAS 2.x Specification
|
|
* for proper setting of this field. For standard SAS Initiator
|
|
* SAS PHY operation it should be 0 for Down-spreading.
|
|
* SAS SSC Tx spread type:
|
|
* Down-spreading SSC = 0
|
|
* Center-spreading SSC = 1
|
|
*/
|
|
U8 ssc_sas_tx_type : 1;
|
|
|
|
/**
|
|
* This field indicates length of the SAS/SATA cable between
|
|
* host and device.
|
|
* This field is used make relationship between analog parameters of
|
|
* the phy in the silicon and length of the cable.
|
|
* Supported length: "short"- up to 3m, "long"- more than 3m
|
|
* This is bit mask field:
|
|
*
|
|
* BIT: 7 6 5 4 3 2 1 0 (LSB)
|
|
* ASSIGNMENT: <-><-><-><-><phy3><phy2><phy1><phy0>
|
|
*
|
|
* For short cable corresponding bit shall be reset,
|
|
* for long cable shall be set.
|
|
*/
|
|
U8 long_cable_selection_mask;
|
|
|
|
} controller;
|
|
|
|
/**
|
|
* Per SAS Port data.
|
|
*/
|
|
struct
|
|
{
|
|
/**
|
|
* This field specifies the phys to be contained inside a port.
|
|
* The bit position in the mask specifies the index of the phy
|
|
* to be contained in the port. Multiple bits (i.e. phys)
|
|
* can be contained in a single port:
|
|
* Bit 0 = This controller's PHY index 0 (0x01)
|
|
* Bit 1 = This controller's PHY index 1 (0x02)
|
|
* Bit 2 = This controller's PHY index 2 (0x04)
|
|
* Bit 3 = This controller's PHY index 3 (0x08)
|
|
*
|
|
* Refer to the mode_type field for rules regarding APC and MPC mode.
|
|
* General rule: For APC mode phy_mask = 0
|
|
*/
|
|
U8 phy_mask;
|
|
|
|
} ports[SCI_MAX_PORTS]; // Up to 4 Ports per SCU controller unit
|
|
|
|
/**
|
|
* Per PHY Parameter data.
|
|
*/
|
|
struct
|
|
{
|
|
/**
|
|
* This field indicates the SAS Address that will be transmitted on
|
|
* this PHY index. The field is defined as a union, however, the
|
|
* OEM should use the U8 array definition when encoding it to ensure
|
|
* correct byte ordering.
|
|
*
|
|
* NOTE: If using APC MODE, along with phy_mask being set to ZERO, the
|
|
* SAS Addresses for all PHYs within a controller group SHALL be the
|
|
* same.
|
|
*/
|
|
union
|
|
{
|
|
/**
|
|
* The array should be stored in little endian order. For example,
|
|
* if the desired SAS Address is 0x50010B90_0003538D, then it
|
|
* should be stored in the following manner:
|
|
* array[0] = 0x90
|
|
* array[1] = 0x0B
|
|
* array[2] = 0x01
|
|
* array[3] = 0x50
|
|
* array[4] = 0x8D
|
|
* array[5] = 0x53
|
|
* array[6] = 0x03
|
|
* array[7] = 0x00
|
|
*/
|
|
U8 array[8];
|
|
/**
|
|
* This is the typedef'd version of the SAS Address used in
|
|
* the SCI Library.
|
|
*/
|
|
SCI_SAS_ADDRESS_T sci_format;
|
|
|
|
} sas_address;
|
|
|
|
/**
|
|
* These are the per PHY equalization settings associated with the
|
|
* AFE XCVR Tx Amplitude and Equalization Control Register Set
|
|
* (0 thru 3).
|
|
*
|
|
* Operational Note: The following Look-Up-Table registers are engaged
|
|
* by the AFE block after the following:
|
|
* - Software programs the Link Layer AFE Look Up Table Control
|
|
* Registers (AFE_LUTCR).
|
|
* - Software sets AFE XCVR Tx Control Register Tx Equalization
|
|
* Enable bit.
|
|
*/
|
|
/**
|
|
* AFE_TX_AMP_CTRL0. This register is associated with AFE_LUTCR
|
|
* LUTSel=00b. It contains the Tx Equalization settings that will be
|
|
* used if a SATA 1.5Gbs or SATA 3.0Gbs device is direct-attached.
|
|
*/
|
|
U32 afe_tx_amp_control0;
|
|
|
|
/**
|
|
* AFE_TX_AMP_CTRL1. This register is associated with AFE_LUTCR
|
|
* LUTSel=01b. It contains the Tx Equalization settings that will
|
|
* be used if a SATA 6.0Gbs device is direct-attached.
|
|
*/
|
|
U32 afe_tx_amp_control1;
|
|
|
|
/**
|
|
* AFE_TX_AMP_CTRL2. This register is associated with AFE_LUTCR
|
|
* LUTSel=10b. It contains the Tx Equalization settings that will
|
|
* be used if a SAS 1.5Gbs or SAS 3.0Gbs device is direct-attached.
|
|
*/
|
|
U32 afe_tx_amp_control2;
|
|
|
|
/**
|
|
* AFE_TX_AMP_CTRL3. This register is associated with AFE_LUTCR
|
|
* LUTSel=11b. It contains the Tx Equalization settings that will
|
|
* be used if a SAS 6.0Gbs device is direct-attached.
|
|
*/
|
|
U32 afe_tx_amp_control3;
|
|
|
|
} phys[SCI_MAX_PHYS]; // 4 PHYs per SCU controller unit
|
|
|
|
} SCI_BIOS_OEM_PARAM_ELEMENT_v_1_2_T;
|
|
|
|
/**
|
|
* @struct SCIC_SDS_OEM_PARAMETERS VER 1.3
|
|
*
|
|
* @brief This structure delineates the various OEM parameters that must
|
|
* be set for the Intel SAS Storage Controller Unit (SCU).
|
|
*/
|
|
typedef struct SCI_BIOS_OEM_PARAM_ELEMENT_v_1_3
|
|
{
|
|
/**
|
|
* Per SCU Controller Data
|
|
*/
|
|
struct
|
|
{
|
|
/**
|
|
* This field indicates the port configuration mode for
|
|
* this controller:
|
|
* Automatic Port Configuration(APC) or
|
|
* Manual Port Configuration (MPC).
|
|
*
|
|
* APC means the Platform OEM expects SCI to configure
|
|
* SAS Ports automatically according to the discovered SAS
|
|
* Address pairs of the endpoints, wide and/or narrow.
|
|
*
|
|
* MPC means the Platform OEM manually defines wide or narrow
|
|
* connectors by apriori assigning PHYs to SAS Ports.
|
|
*
|
|
* By default, the mode type is APC
|
|
* in APC mode, if ANY of the phy mask is non-zero,
|
|
* SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned
|
|
* from scic_oem_parameters_set AND the default oem
|
|
* configuration will be applied
|
|
* in MPC mode, if ALL of the phy masks are zero,
|
|
* SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned
|
|
* from scic_oem_parameters_set AND the default oem
|
|
* configuration will be applied
|
|
*/
|
|
U8 mode_type;
|
|
|
|
/**
|
|
* This field specifies the maximum number of direct attached
|
|
* devices the OEM will allow to have powered up simultaneously
|
|
* on this controller. This allows the OEM to avoid exceeding
|
|
* power supply limits for this platform. A value of zero
|
|
* indicates there are no restrictions.
|
|
*/
|
|
U8 max_number_concurrent_device_spin_up;
|
|
|
|
/**
|
|
* This bitfield indicates the OEM's desired default Tx
|
|
* Spread Spectrum Clocking (SSC) settings for SATA and SAS.
|
|
* NOTE: Default SSC Modulation Frequency is 31.5KHz.
|
|
*--------------------------------------------------------------------*/
|
|
/**
|
|
* NOTE: Max spread for SATA is +0 / -5000 PPM.
|
|
* Down-spreading SSC (only method allowed for SATA):
|
|
* SATA SSC Tx Disabled = 0x0
|
|
* SATA SSC Tx at +0 / -1419 PPM Spread = 0x2
|
|
* SATA SSC Tx at +0 / -2129 PPM Spread = 0x3
|
|
* SATA SSC Tx at +0 / -4257 PPM Spread = 0x6
|
|
* SATA SSC Tx at +0 / -4967 PPM Spread = 0x7
|
|
*/
|
|
U8 ssc_sata_tx_spread_level : 4;
|
|
|
|
/**
|
|
* SAS SSC Tx Disabled = 0x0
|
|
*
|
|
* NOTE: Max spread for SAS down-spreading +0 / -2300 PPM
|
|
* Down-spreading SSC:
|
|
* SAS SSC Tx at +0 / -1419 PPM Spread = 0x2
|
|
* SAS SSC Tx at +0 / -2129 PPM Spread = 0x3
|
|
*
|
|
* NOTE: Max spread for SAS center-spreading +2300 / -2300 PPM
|
|
* Center-spreading SSC:
|
|
* SAS SSC Tx at +1064 / -1064 PPM Spread = 0x3
|
|
* SAS SSC Tx at +2129 / -2129 PPM Spread = 0x6
|
|
*/
|
|
U8 ssc_sas_tx_spread_level : 3;
|
|
/**
|
|
* NOTE: Refer to the SSC section of the SAS 2.x Specification
|
|
* for proper setting of this field. For standard SAS Initiator
|
|
* SAS PHY operation it should be 0 for Down-spreading.
|
|
* SAS SSC Tx spread type:
|
|
* Down-spreading SSC = 0
|
|
* Center-spreading SSC = 1
|
|
*/
|
|
U8 ssc_sas_tx_type : 1;
|
|
|
|
/**
|
|
* This field indicates length of the SAS/SATA cable between
|
|
* host and device.
|
|
* This field is used make relationship between analog parameters of
|
|
* the phy in the silicon and length of the cable.
|
|
* Supported cable attenuation levels:
|
|
* "short"- up to 3m, "medium"-3m to 6m, and "long"- more than 6m
|
|
* This is bit mask field:
|
|
*
|
|
* BIT: (MSB) 7 6 5 4
|
|
* ASSIGNMENT: <phy3><phy2><phy1><phy0> - Medium cable length assignment
|
|
* BIT: 3 2 1 0 (LSB)
|
|
* ASSIGNMENT: <phy3><phy2><phy1><phy0> - Long cable length assignment
|
|
*
|
|
* BITS 7-4 are set when the cable length is assigned to medium
|
|
* BITS 3-0 are set when the cable length is assigned to long
|
|
* The BIT positions are clear when the cable length is assigned to short
|
|
* Setting the bits for both long and medium cable length is undefined.
|
|
*
|
|
* A value of 0x84 would assign
|
|
* phy3 - medium
|
|
* phy2 - long
|
|
* phy1 - short
|
|
* phy0 - short
|
|
*/
|
|
U8 cable_selection_mask;
|
|
|
|
} controller;
|
|
|
|
/**
|
|
* Per SAS Port data.
|
|
*/
|
|
struct
|
|
{
|
|
/**
|
|
* This field specifies the phys to be contained inside a port.
|
|
* The bit position in the mask specifies the index of the phy
|
|
* to be contained in the port. Multiple bits (i.e. phys)
|
|
* can be contained in a single port:
|
|
* Bit 0 = This controller's PHY index 0 (0x01)
|
|
* Bit 1 = This controller's PHY index 1 (0x02)
|
|
* Bit 2 = This controller's PHY index 2 (0x04)
|
|
* Bit 3 = This controller's PHY index 3 (0x08)
|
|
*
|
|
* Refer to the mode_type field for rules regarding APC and MPC mode.
|
|
* General rule: For APC mode phy_mask = 0
|
|
*/
|
|
U8 phy_mask;
|
|
|
|
} ports[SCI_MAX_PORTS]; // Up to 4 Ports per SCU controller unit
|
|
|
|
/**
|
|
* Per PHY Parameter data.
|
|
*/
|
|
struct
|
|
{
|
|
/**
|
|
* This field indicates the SAS Address that will be transmitted on
|
|
* this PHY index. The field is defined as a union, however, the
|
|
* OEM should use the U8 array definition when encoding it to ensure
|
|
* correct byte ordering.
|
|
*
|
|
* NOTE: If using APC MODE, along with phy_mask being set to ZERO, the
|
|
* SAS Addresses for all PHYs within a controller group SHALL be the
|
|
* same.
|
|
*/
|
|
union
|
|
{
|
|
/**
|
|
* The array should be stored in little endian order. For example,
|
|
* if the desired SAS Address is 0x50010B90_0003538D, then it
|
|
* should be stored in the following manner:
|
|
* array[0] = 0x90
|
|
* array[1] = 0x0B
|
|
* array[2] = 0x01
|
|
* array[3] = 0x50
|
|
* array[4] = 0x8D
|
|
* array[5] = 0x53
|
|
* array[6] = 0x03
|
|
* array[7] = 0x00
|
|
*/
|
|
U8 array[8];
|
|
/**
|
|
* This is the typedef'd version of the SAS Address used in
|
|
* the SCI Library.
|
|
*/
|
|
SCI_SAS_ADDRESS_T sci_format;
|
|
|
|
} sas_address;
|
|
|
|
/**
|
|
* These are the per PHY equalization settings associated with the
|
|
* AFE XCVR Tx Amplitude and Equalization Control Register Set
|
|
* (0 thru 3).
|
|
*
|
|
* Operational Note: The following Look-Up-Table registers are engaged
|
|
* by the AFE block after the following:
|
|
* - Software programs the Link Layer AFE Look Up Table Control
|
|
* Registers (AFE_LUTCR).
|
|
* - Software sets AFE XCVR Tx Control Register Tx Equalization
|
|
* Enable bit.
|
|
*/
|
|
/**
|
|
* AFE_TX_AMP_CTRL0. This register is associated with AFE_LUTCR
|
|
* LUTSel=00b. It contains the Tx Equalization settings that will be
|
|
* used if a SATA 1.5Gbs or SATA 3.0Gbs device is direct-attached.
|
|
*/
|
|
U32 afe_tx_amp_control0;
|
|
|
|
/**
|
|
* AFE_TX_AMP_CTRL1. This register is associated with AFE_LUTCR
|
|
* LUTSel=01b. It contains the Tx Equalization settings that will
|
|
* be used if a SATA 6.0Gbs device is direct-attached.
|
|
*/
|
|
U32 afe_tx_amp_control1;
|
|
|
|
/**
|
|
* AFE_TX_AMP_CTRL2. This register is associated with AFE_LUTCR
|
|
* LUTSel=10b. It contains the Tx Equalization settings that will
|
|
* be used if a SAS 1.5Gbs or SAS 3.0Gbs device is direct-attached.
|
|
*/
|
|
U32 afe_tx_amp_control2;
|
|
|
|
/**
|
|
* AFE_TX_AMP_CTRL3. This register is associated with AFE_LUTCR
|
|
* LUTSel=11b. It contains the Tx Equalization settings that will
|
|
* be used if a SAS 6.0Gbs device is direct-attached.
|
|
*/
|
|
U32 afe_tx_amp_control3;
|
|
|
|
} phys[SCI_MAX_PHYS]; // 4 PHYs per SCU controller unit
|
|
|
|
} SCI_BIOS_OEM_PARAM_ELEMENT_v_1_3_T;
|
|
|
|
/**
|
|
* @struct SCI_BIOS_OEM_PARAM_BLOCK
|
|
*
|
|
* @brief This structure defines the OEM Parameter block as it will be stored
|
|
* in the last 512 bytes of the PDR region in the SPI flash. It must be
|
|
* unpacked or pack(1).
|
|
*/
|
|
typedef struct SCI_BIOS_OEM_PARAM_BLOCK
|
|
{
|
|
/**
|
|
* OEM Parameter Block header.
|
|
*/
|
|
SCI_BIOS_OEM_PARAM_BLOCK_HDR_T header;
|
|
|
|
/**
|
|
* Per controller element descriptor containing the controller's
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* parameter data. The prototype defines just one of these descriptors,
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* however, the actual runtime number is determined by the num_elements
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* field in the header.
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*/
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SCI_BIOS_OEM_PARAM_ELEMENT_T controller_element[1];
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} SCI_BIOS_OEM_PARAM_BLOCK_T;
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#ifdef __cplusplus
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}
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#endif // __cplusplus
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#endif // _SCU_BIOS_DEFINITIONS_H_
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