453 lines
13 KiB
C
453 lines
13 KiB
C
/*
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* Copyright (c) 2004-05 Applied Micro Circuits Corporation.
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* Copyright (c) 2004-05 Vinod Kashyap
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* AMCC'S 3ware driver for 9000 series storage controllers.
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*
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* Author: Vinod Kashyap
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*/
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#ifndef TW_CL_FWIF_H
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#define TW_CL_FWIF_H
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/*
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* Macros and data structures for interfacing with the firmware.
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*/
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/* Register offsets from base address. */
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#define TWA_CONTROL_REGISTER_OFFSET 0x0
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#define TWA_STATUS_REGISTER_OFFSET 0x4
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#define TWA_COMMAND_QUEUE_OFFSET 0x8
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#define TWA_RESPONSE_QUEUE_OFFSET 0xC
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#define TWA_COMMAND_QUEUE_OFFSET_LOW 0x20
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#define TWA_COMMAND_QUEUE_OFFSET_HIGH 0x24
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#define TWA_LARGE_RESPONSE_QUEUE_OFFSET 0x30
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/* Control register bit definitions. */
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#define TWA_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020
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#define TWA_CONTROL_DISABLE_INTERRUPTS 0x00000040
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#define TWA_CONTROL_ENABLE_INTERRUPTS 0x00000080
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#define TWA_CONTROL_ISSUE_SOFT_RESET 0x00000100
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#define TWA_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000
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#define TWA_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000
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#define TWA_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000
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#define TWA_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000
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#define TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000
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#define TWA_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000
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#define TWA_CONTROL_CLEAR_PCI_ABORT 0x00100000
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#define TWA_CONTROL_CLEAR_QUEUE_ERROR 0x00400000
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#define TWA_CONTROL_CLEAR_PARITY_ERROR 0x00800000
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/* Status register bit definitions. */
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#define TWA_STATUS_ROM_BIOS_IN_SBUF 0x00000002
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#define TWA_STATUS_COMMAND_QUEUE_EMPTY 0x00001000
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#define TWA_STATUS_MICROCONTROLLER_READY 0x00002000
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#define TWA_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000
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#define TWA_STATUS_COMMAND_QUEUE_FULL 0x00008000
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#define TWA_STATUS_RESPONSE_INTERRUPT 0x00010000
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#define TWA_STATUS_COMMAND_INTERRUPT 0x00020000
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#define TWA_STATUS_ATTENTION_INTERRUPT 0x00040000
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#define TWA_STATUS_HOST_INTERRUPT 0x00080000
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#define TWA_STATUS_PCI_ABORT_INTERRUPT 0x00100000
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#define TWA_STATUS_MICROCONTROLLER_ERROR 0x00200000
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#define TWA_STATUS_QUEUE_ERROR_INTERRUPT 0x00400000
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#define TWA_STATUS_PCI_PARITY_ERROR_INTERRUPT 0x00800000
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#define TWA_STATUS_MINOR_VERSION_MASK 0x0F000000
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#define TWA_STATUS_MAJOR_VERSION_MASK 0xF0000000
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#define TWA_STATUS_EXPECTED_BITS 0x00002000
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#define TWA_STATUS_UNEXPECTED_BITS 0x00F00000
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/* PCI related defines. */
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#define TWA_IO_CONFIG_REG 0x10
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#define TWA_PCI_CONFIG_CLEAR_PARITY_ERROR 0xc100
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#define TWA_PCI_CONFIG_CLEAR_PCI_ABORT 0x2000
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#define TWA_RESET_PHASE1_NOTIFICATION_RESPONSE 0xFFFF
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#define TWA_RESET_PHASE1_WAIT_TIME_MS 500
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/* Command packet opcodes. */
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#define TWA_FW_CMD_NOP 0x00
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#define TWA_FW_CMD_INIT_CONNECTION 0x01
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#define TWA_FW_CMD_READ 0x02
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#define TWA_FW_CMD_WRITE 0x03
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#define TWA_FW_CMD_READVERIFY 0x04
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#define TWA_FW_CMD_VERIFY 0x05
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#define TWA_FW_CMD_ZEROUNIT 0x08
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#define TWA_FW_CMD_REPLACEUNIT 0x09
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#define TWA_FW_CMD_HOTSWAP 0x0A
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#define TWA_FW_CMD_SELFTESTS 0x0B
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#define TWA_FW_CMD_SYNC_PARAM 0x0C
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#define TWA_FW_CMD_REORDER_UNITS 0x0D
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#define TWA_FW_CMD_EXECUTE_SCSI 0x10
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#define TWA_FW_CMD_ATA_PASSTHROUGH 0x11
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#define TWA_FW_CMD_GET_PARAM 0x12
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#define TWA_FW_CMD_SET_PARAM 0x13
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#define TWA_FW_CMD_CREATEUNIT 0x14
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#define TWA_FW_CMD_DELETEUNIT 0x15
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#define TWA_FW_CMD_DOWNLOAD_FIRMWARE 0x16
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#define TWA_FW_CMD_REBUILDUNIT 0x17
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#define TWA_FW_CMD_POWER_MANAGEMENT 0x18
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#define TWA_FW_CMD_REMOTE_PRINT 0x1B
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#define TWA_FW_CMD_HARD_RESET_FIRMWARE 0x1C
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#define TWA_FW_CMD_DEBUG 0x1D
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#define TWA_FW_CMD_DIAGNOSTICS 0x1F
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/* Misc defines. */
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#define TWA_BUNDLED_FW_VERSION_STRING "3.02.00.004"
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#define TWA_SHUTDOWN_MESSAGE_CREDITS 0x001
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#define TWA_64BIT_SG_ADDRESSES 0x00000001
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#define TWA_EXTENDED_INIT_CONNECT 0x00000002
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#define TWA_BASE_MODE 1
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#define TWA_BASE_FW_SRL 24
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#define TWA_BASE_FW_BRANCH 0
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#define TWA_BASE_FW_BUILD 1
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#define TWA_CURRENT_FW_SRL 30
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#define TWA_CURRENT_FW_BRANCH_9K 4
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#define TWA_CURRENT_FW_BUILD_9K 8
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#define TWA_CURRENT_FW_BRANCH_9K_X 8
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#define TWA_CURRENT_FW_BUILD_9K_X 4
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#define TWA_MULTI_LUN_FW_SRL 28
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#define TWA_ARCH_ID_9K 0x5 /* 9000 PCI controllers */
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#define TWA_ARCH_ID_9K_X 0x6 /* 9000 PCI-X controllers */
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#define TWA_CTLR_FW_SAME_OR_NEWER 0x00000001
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#define TWA_CTLR_FW_COMPATIBLE 0x00000002
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#define TWA_BUNDLED_FW_SAFE_TO_FLASH 0x00000004
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#define TWA_CTLR_FW_RECOMMENDS_FLASH 0x00000008
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#define TWA_SENSE_DATA_LENGTH 18
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#define TWA_ARCH_ID(device_id) \
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(((device_id) == TW_CL_DEVICE_ID_9K) ? TWA_ARCH_ID_9K : \
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TWA_ARCH_ID_9K_X)
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#define TWA_CURRENT_FW_BRANCH(arch_id) \
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(((arch_id) == TWA_ARCH_ID_9K) ? TWA_CURRENT_FW_BRANCH_9K : \
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TWA_CURRENT_FW_BRANCH_9K_X)
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#define TWA_CURRENT_FW_BUILD(arch_id) \
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(((arch_id) == TWA_ARCH_ID_9K) ? TWA_CURRENT_FW_BUILD_9K : \
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TWA_CURRENT_FW_BUILD_9K_X)
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/*
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* All SG addresses and DMA'able memory allocated by the OSL should be
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* TWA_ALIGNMENT bytes aligned, and have a size that is a multiple of
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* TWA_SG_ELEMENT_SIZE_FACTOR.
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*/
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#define TWA_ALIGNMENT(device_id) 0x4
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#define TWA_SG_ELEMENT_SIZE_FACTOR(device_id) \
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(((device_id) == TW_CL_DEVICE_ID_9K) ? 512 : 4)
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/*
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* Some errors of interest (in cmd_hdr->status_block.error) when a command
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* is completed by the firmware with a bad status.
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*/
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#define TWA_ERROR_LOGICAL_UNIT_NOT_SUPPORTED 0x010a
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#define TWA_ERROR_UNIT_OFFLINE 0x0128
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#define TWA_ERROR_MORE_DATA 0x0231
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/* AEN codes of interest. */
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#define TWA_AEN_QUEUE_EMPTY 0x00
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#define TWA_AEN_SOFT_RESET 0x01
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#define TWA_AEN_SYNC_TIME_WITH_HOST 0x31
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/* Table #'s and id's of parameters of interest in firmware's param table. */
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#define TWA_PARAM_VERSION_TABLE 0x0402
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#define TWA_PARAM_VERSION_FW 3 /* firmware version [16] */
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#define TWA_PARAM_VERSION_BIOS 4 /* BIOSs version [16] */
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#define TWA_PARAM_CTLR_MODEL 8 /* Controller model [16] */
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#define TWA_PARAM_CONTROLLER_TABLE 0x0403
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#define TWA_PARAM_CONTROLLER_PORT_COUNT 3 /* number of ports [1] */
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#define TWA_PARAM_TIME_TABLE 0x40A
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#define TWA_PARAM_TIME_SCHED_TIME 0x3
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#define TWA_9K_PARAM_DESCRIPTOR 0x8000
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#pragma pack(1)
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/* 7000 structures. */
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struct tw_cl_command_init_connect {
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TW_UINT8 res1__opcode; /* 3:5 */
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TW_UINT8 size;
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TW_UINT8 request_id;
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TW_UINT8 res2;
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TW_UINT8 status;
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TW_UINT8 flags;
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TW_UINT16 message_credits;
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TW_UINT32 features;
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TW_UINT16 fw_srl;
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TW_UINT16 fw_arch_id;
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TW_UINT16 fw_branch;
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TW_UINT16 fw_build;
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TW_UINT32 result;
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};
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/* Structure for downloading firmware onto the controller. */
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struct tw_cl_command_download_firmware {
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TW_UINT8 sgl_off__opcode;/* 3:5 */
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TW_UINT8 size;
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TW_UINT8 request_id;
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TW_UINT8 unit;
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TW_UINT8 status;
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TW_UINT8 flags;
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TW_UINT16 param;
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TW_UINT8 sgl[1];
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};
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/* Structure for hard resetting the controller. */
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struct tw_cl_command_reset_firmware {
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TW_UINT8 res1__opcode; /* 3:5 */
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TW_UINT8 size;
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TW_UINT8 request_id;
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TW_UINT8 unit;
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TW_UINT8 status;
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TW_UINT8 flags;
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TW_UINT8 res2;
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TW_UINT8 param;
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};
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/* Structure for sending get/set param commands. */
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struct tw_cl_command_param {
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TW_UINT8 sgl_off__opcode;/* 3:5 */
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TW_UINT8 size;
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TW_UINT8 request_id;
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TW_UINT8 host_id__unit; /* 4:4 */
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TW_UINT8 status;
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TW_UINT8 flags;
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TW_UINT16 param_count;
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TW_UINT8 sgl[1];
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};
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/* Generic command packet. */
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struct tw_cl_command_generic {
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TW_UINT8 sgl_off__opcode;/* 3:5 */
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TW_UINT8 size;
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TW_UINT8 request_id;
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TW_UINT8 host_id__unit; /* 4:4 */
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TW_UINT8 status;
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TW_UINT8 flags;
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TW_UINT16 count; /* block cnt, parameter cnt, message credits */
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};
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/* Command packet header. */
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struct tw_cl_command_header {
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TW_UINT8 sense_data[TWA_SENSE_DATA_LENGTH];
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struct {
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TW_INT8 reserved[4];
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TW_UINT16 error;
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TW_UINT8 padding;
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TW_UINT8 res__severity; /* 5:3 */
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} status_block;
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TW_UINT8 err_specific_desc[98];
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struct {
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TW_UINT8 size_header;
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TW_UINT16 reserved;
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TW_UINT8 size_sense;
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} header_desc;
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};
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/* 7000 Command packet. */
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union tw_cl_command_7k {
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struct tw_cl_command_init_connect init_connect;
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struct tw_cl_command_download_firmware download_fw;
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struct tw_cl_command_reset_firmware reset_fw;
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struct tw_cl_command_param param;
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struct tw_cl_command_generic generic;
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TW_UINT8 padding[1024 - sizeof(struct tw_cl_command_header)];
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};
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/* 9000 Command Packet. */
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struct tw_cl_command_9k {
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TW_UINT8 res__opcode; /* 3:5 */
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TW_UINT8 unit;
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TW_UINT16 lun_l4__req_id; /* 4:12 */
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TW_UINT8 status;
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TW_UINT8 sgl_offset; /* offset (in bytes) to sg_list, from the
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end of sgl_entries */
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TW_UINT16 lun_h4__sgl_entries;
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TW_UINT8 cdb[16];
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TW_UINT8 sg_list[872];/* total struct size =
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1024-sizeof(cmd_hdr) */
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};
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/* Full command packet. */
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struct tw_cl_command_packet {
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struct tw_cl_command_header cmd_hdr;
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union {
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union tw_cl_command_7k cmd_pkt_7k;
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struct tw_cl_command_9k cmd_pkt_9k;
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} command;
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};
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/* Structure describing payload for get/set param commands. */
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struct tw_cl_param_9k {
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TW_UINT16 table_id;
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TW_UINT8 parameter_id;
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TW_UINT8 reserved;
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TW_UINT16 parameter_size_bytes;
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TW_UINT16 parameter_actual_size_bytes;
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TW_UINT8 data[1];
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};
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#pragma pack()
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/* Functions to read from, and write to registers */
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#define TW_CLI_WRITE_CONTROL_REGISTER(ctlr_handle, value) \
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tw_osl_write_reg(ctlr_handle, TWA_CONTROL_REGISTER_OFFSET, value, 4)
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#define TW_CLI_READ_STATUS_REGISTER(ctlr_handle) \
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tw_osl_read_reg(ctlr_handle, TWA_STATUS_REGISTER_OFFSET, 4)
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#define TW_CLI_WRITE_COMMAND_QUEUE(ctlr_handle, value) do { \
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if (ctlr->flags & TW_CL_64BIT_ADDRESSES) { \
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/* First write the low 4 bytes, then the high 4. */ \
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tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET_LOW, \
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(TW_UINT32)(value), 4); \
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tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET_HIGH,\
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(TW_UINT32)(((TW_UINT64)value)>>32), 4); \
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} else \
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tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET, \
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(TW_UINT32)(value), 4); \
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} while (0)
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#define TW_CLI_READ_RESPONSE_QUEUE(ctlr_handle) \
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tw_osl_read_reg(ctlr_handle, TWA_RESPONSE_QUEUE_OFFSET, 4)
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#define TW_CLI_READ_LARGE_RESPONSE_QUEUE(ctlr_handle) \
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tw_osl_read_reg(ctlr_handle, TWA_LARGE_RESPONSE_QUEUE_OFFSET, 4)
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#define TW_CLI_SOFT_RESET(ctlr) \
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TW_CLI_WRITE_CONTROL_REGISTER(ctlr, \
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TWA_CONTROL_ISSUE_SOFT_RESET | \
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TWA_CONTROL_CLEAR_HOST_INTERRUPT | \
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TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT | \
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TWA_CONTROL_MASK_COMMAND_INTERRUPT | \
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TWA_CONTROL_MASK_RESPONSE_INTERRUPT | \
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TWA_CONTROL_DISABLE_INTERRUPTS)
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/* Detect inconsistencies in the status register. */
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#define TW_CLI_STATUS_ERRORS(x) \
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((x & TWA_STATUS_UNEXPECTED_BITS) && \
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(x & TWA_STATUS_MICROCONTROLLER_READY))
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/*
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* Functions for making transparent, the bit fields in firmware
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* interface structures.
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*/
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#define BUILD_SGL_OFF__OPCODE(sgl_off, opcode) \
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((sgl_off << 5) & 0xE0) | (opcode & 0x1F) /* 3:5 */
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#define BUILD_RES__OPCODE(res, opcode) \
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((res << 5) & 0xE0) | (opcode & 0x1F) /* 3:5 */
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#define BUILD_HOST_ID__UNIT(host_id, unit) \
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((host_id << 4) & 0xF0) | (unit & 0xF) /* 4:4 */
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#define BUILD_RES__SEVERITY(res, severity) \
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((res << 3) & 0xF8) | (severity & 0x7) /* 5:3 */
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#define BUILD_LUN_L4__REQ_ID(lun, req_id) \
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(((lun << 12) & 0xF000) | (req_id & 0xFFF)) /* 4:12 */
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#define BUILD_LUN_H4__SGL_ENTRIES(lun, sgl_entries) \
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(((lun << 8) & 0xF000) | (sgl_entries & 0xFFF)) /* 4:12 */
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#define GET_OPCODE(sgl_off__opcode) \
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(sgl_off__opcode & 0x1F) /* 3:5 */
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#define GET_SGL_OFF(sgl_off__opcode) \
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((sgl_off__opcode >> 5) & 0x7) /* 3:5 */
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#define GET_UNIT(host_id__unit) \
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(host_id__unit & 0xF) /* 4:4 */
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#define GET_HOST_ID(host_id__unit) \
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((host_id__unit >> 4) & 0xF) /* 4:4 */
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#define GET_SEVERITY(res__severity) \
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(res__severity & 0x7) /* 5:3 */
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#define GET_RESP_ID(undef2__resp_id__undef1) \
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((undef2__resp_id__undef1 >> 4) & 0xFF) /* 20:8:4 */
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#define GET_RESP_ID_9K_X(undef2__resp_id) \
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((undef2__resp_id) & 0xFFF) /* 20:12 */
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#define GET_LARGE_RESP_ID(misc__large_resp_id) \
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((misc__large_resp_id) & 0xFFFF) /* 16:16 */
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#define GET_REQ_ID(lun_l4__req_id) \
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(lun_l4__req_id & 0xFFF) /* 4:12 */
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#define GET_LUN_L4(lun_l4__req_id) \
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((lun_l4__req_id >> 12) & 0xF) /* 4:12 */
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#define GET_SGL_ENTRIES(lun_h4__sgl_entries) \
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(lun_h4__sgl_entries & 0xFFF) /* 4:12 */
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#define GET_LUN_H4(lun_h4__sgl_entries) \
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((lun_h4__sgl_entries >> 12) & 0xF) /* 4:12 */
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#endif /* TW_CL_FWIF_H */
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