c5cb388883
New sequencer assembler for the aic7xxx adapters. This assembler performs some amount of register type checking, allows bit manipulation of symbolic constants, and generates "patch tables" for conditionalized downloading of portions of the program. This makes it easier to take full advantage of the different features of the aic7xxx cards without imposing run time penalies or being bound to the small memory footprints of the low end cards for features like target mode. aic7xxx.reg: New, assembler parsed, register definitions fo the aic7xxx cards. This was done primarily in anticipation of 7810 support which will have a different register layout, but should be able to use the same assembler. The kernel aic7xxx driver consumes a generated file in the compile directory to get the definitions of the register locations. aic7xxx.seq: Convert to the slighly different syntax of the new assembler. Conditionalize SCB_PAGING, ultra, and twin features which shaves quite a bit of space once the program is downloaded. Add code to leave the selection hardware enabled during reconnects that win bus arbitration. This ensures that we will rearbitrate as soon as the bus goes free instead of delaying for a bit. When we expect the bus to go free, perform all of the cleanup associated with that event "up front" and enter a loop awaiting bus free. If we see a REQ first, complain, but attempt to continue. This will hopefully address, or at least help diagnose, the "target didn't send identify" messages that have been reported. Spelling corrections obtained from NetBSD.
90 lines
2.7 KiB
C
90 lines
2.7 KiB
C
/*
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* Instruction formats for the sequencer program downloaded to
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* Aic7xxx SCSI host adapters
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*
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* Copyright (c) 1997 Justin T. Gibbs.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id$
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*/
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struct ins_format1 {
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u_int8_t immediate;
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u_int8_t source;
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u_int8_t destination;
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u_int8_t opcode_ret;
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};
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struct ins_format2 {
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u_int8_t shift_control;
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u_int8_t source;
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u_int8_t destination;
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u_int8_t opcode_ret;
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#define RETURN_BIT 0x01
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};
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struct ins_format3 {
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u_int8_t immediate;
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u_int8_t source;
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u_int8_t address;
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u_int8_t opcode_addr;
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#define ADDR_HIGH_BIT 0x01
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};
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struct instruction {
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union {
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struct ins_format1 format1;
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struct ins_format2 format2;
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struct ins_format3 format3;
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u_int8_t bytes[4];
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} format;
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u_int srcline;
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struct symbol *patch_label;
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STAILQ_ENTRY(instruction) links;
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};
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#define AIC_OP_OR 0x0
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#define AIC_OP_AND 0x1
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#define AIC_OP_XOR 0x2
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#define AIC_OP_ADD 0x3
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#define AIC_OP_ADC 0x4
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#define AIC_OP_ROL 0x5
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#define AIC_OP_JMP 0x8
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#define AIC_OP_JC 0x9
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#define AIC_OP_JNC 0xa
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#define AIC_OP_CALL 0xb
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#define AIC_OP_JNE 0xc
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#define AIC_OP_JNZ 0xd
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#define AIC_OP_JE 0xe
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#define AIC_OP_JZ 0xf
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/* Pseudo Ops */
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#define AIC_OP_SHL 0x10
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#define AIC_OP_SHR 0x20
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#define AIC_OP_ROR 0x30
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