f4b37ed0f8
Import from vendor-sys/alpine-hal/2.7 SVN rev.: 285432 HAL version: 2.7 Obtained from: Semihalf Sponsored by: Annapurna Labs
223 lines
7.5 KiB
C
223 lines
7.5 KiB
C
/*-
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********************************************************************************
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Copyright (C) 2015 Annapurna Labs Ltd.
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This file may be licensed under the terms of the Annapurna Labs Commercial
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License Agreement.
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Alternatively, this file can be distributed under the terms of the GNU General
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Public License V2 as published by the Free Software Foundation and can be
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found at http://www.gnu.org/licenses/gpl-2.0.html
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Alternatively, redistribution and use in source and binary forms, with or
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without modification, are permitted provided that the following conditions are
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met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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/**
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* @defgroup group_interrupts Common I/O Fabric Interrupt Controller
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* This HAL provides the API for programming the Common I/O Fabric Interrupt
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* Controller (IOFIC) found in most of the units attached to the I/O Fabric of
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* Alpine platform
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* @{
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* @file al_hal_iofic.h
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*
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* @brief Header file for the interrupt controller that's embedded in various units
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*
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*/
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#ifndef __AL_HAL_IOFIC_H__
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#define __AL_HAL_IOFIC_H__
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#include <al_hal_common.h>
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/* *INDENT-OFF* */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* *INDENT-ON* */
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#define AL_IOFIC_MAX_GROUPS 4
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/*
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* Configurations
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*/
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/**
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* Configure the interrupt controller registers, actual interrupts are still
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* masked at this stage.
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*
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* @param regs_base regs pointer to interrupt controller registers
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* @param group the interrupt group.
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* @param flags flags of Interrupt Control Register
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*
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* @return 0 on success. -EINVAL otherwise.
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*/
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int al_iofic_config(void __iomem *regs_base, int group,
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uint32_t flags);
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/**
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* configure the moderation timer resolution for a given group
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* Applies for both msix and legacy mode.
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*
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* @param regs_base pointer to unit registers
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* @param group the interrupt group
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* @param resolution resolution of the timer interval, the resolution determines the rate
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* of decrementing the interval timer, setting value N means that the interval
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* timer will be decremented each (N+1) * (0.68) micro seconds.
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*
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* @return 0 on success. -EINVAL otherwise.
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*/
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int al_iofic_moder_res_config(void __iomem *regs_base, int group,
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uint8_t resolution);
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/**
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* configure the moderation timer interval for a given legacy interrupt group
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*
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* @param regs_base regs pointer to unit registers
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* @param group the interrupt group
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* @param interval between interrupts in resolution units. 0 disable
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*
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* @return 0 on success. -EINVAL otherwise.
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*/
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int al_iofic_legacy_moder_interval_config(void __iomem *regs_base, int group,
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uint8_t interval);
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/**
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* configure the moderation timer interval for a given msix vector
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*
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* @param regs_base pointer to unit registers
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* @param group the interrupt group
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* @param vector vector index
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* @param interval interval between interrupts, 0 disable
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*
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* @return 0 on success. -EINVAL otherwise.
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*/
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int al_iofic_msix_moder_interval_config(void __iomem *regs_base, int group,
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uint8_t vector, uint8_t interval);
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/**
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* configure the vmid attributes for a given msix vector.
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*
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* @param group the interrupt group
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* @param vector index
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* @param vmid the vmid value
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* @param vmid_en take vmid from the intc
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*
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* @return 0 on success. -EINVAL otherwise.
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*/
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int al_iofic_msix_vmid_attributes_config(void __iomem *regs_base, int group,
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uint8_t vector, uint32_t vmid, uint8_t vmid_en);
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/**
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* return the offset of the unmask register for a given group.
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* this function can be used when the upper layer wants to directly
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* access the unmask regiter and bypass the al_iofic_unmask() API.
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*
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* @param regs_base regs pointer to unit registers
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* @param group the interrupt group
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* @return the offset of the unmask register.
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*/
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uint32_t __iomem * al_iofic_unmask_offset_get(void __iomem *regs_base, int group);
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/**
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* unmask specific interrupts for a given group
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* this functions guarantees atomic operations, it is performance optimized as
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* it will not require read-modify-write. The unmask done using the interrupt
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* mask clear register, so it's safe to call it while the mask is changed by
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* the HW (auto mask) or another core.
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*
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* @param regs_base pointer to unit registers
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* @param group the interrupt group
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* @param mask bitwise of interrupts to unmask, set bits will be unmasked.
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*/
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void al_iofic_unmask(void __iomem *regs_base, int group, uint32_t mask);
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/**
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* mask specific interrupts for a given group
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* this functions modifies interrupt mask register, the callee must make sure
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* the mask is not changed by another cpu.
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*
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* @param regs_base pointer to unit registers
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* @param group the interrupt group
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* @param mask bitwise of interrupts to mask, set bits will be masked.
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*/
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void al_iofic_mask(void __iomem *regs_base, int group, uint32_t mask);
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/**
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* read the mask register for a given group
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* this functions return the interrupt mask register
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*
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* @param regs_base pointer to unit registers
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* @param group the interrupt group
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*/
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uint32_t al_iofic_read_mask(void __iomem *regs_base, int group);
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/**
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* read interrupt cause register for a given group
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* this will clear the set bits if the Clear on Read mode enabled.
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* @param regs_base pointer to unit registers
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* @param group the interrupt group
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*/
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uint32_t al_iofic_read_cause(void __iomem *regs_base, int group);
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/**
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* clear bits in the interrupt cause register for a given group
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*
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* @param regs_base pointer to unit registers
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* @param group the interrupt group
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* @param mask bitwise of bits to be cleared, set bits will be cleared.
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*/
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void al_iofic_clear_cause(void __iomem *regs_base, int group, uint32_t mask);
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/**
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* set the cause register for a given group
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* this function set the cause register. It will generate an interrupt (if
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* the the interrupt isn't masked )
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*
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* @param regs_base pointer to unit registers
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* @param group the interrupt group
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* @param mask bitwise of bits to be set.
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*/
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void al_iofic_set_cause(void __iomem *regs_base, int group, uint32_t mask);
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/**
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* unmask specific interrupts from aborting the udma a given group
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*
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* @param regs_base pointer to unit registers
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* @param group the interrupt group
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* @param mask bitwise of interrupts to mask
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*/
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void al_iofic_abort_mask(void __iomem *regs_base, int group, uint32_t mask);
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/**
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* trigger all interrupts that are waiting for moderation timers to expire
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*
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* @param regs_base pointer to unit registers
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* @param group the interrupt group
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*/
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void al_iofic_interrupt_moderation_reset(void __iomem *regs_base, int group);
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#endif
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/** @} end of interrupt controller group */
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