6b7ba54456
The PQ3 is a high performance integrated communications processing system based on the e500 core, which is an embedded RISC processor that implements the 32-bit Book E definition of the PowerPC architecture. For details refer to: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8555E This port was tested and successfully run on the following members of the PQ3 family: MPC8533, MPC8541, MPC8548, MPC8555. The following major integrated peripherals are supported: * On-chip peripherals bus * OpenPIC interrupt controller * UART * Ethernet (TSEC) * Host/PCI bridge * QUICC engine (SCC functionality) This commit brings the main functionality and will be followed by individual drivers that are logically separate from this base. Approved by: cognet (mentor) Obtained from: Juniper, Semihalf MFp4: e500
89 lines
2.7 KiB
C
89 lines
2.7 KiB
C
/*-
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* Copyright 2006 by Juniper Networks.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/tty.h>
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#include <machine/bus.h>
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#include <machine/ocpbus.h>
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_bus.h>
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static int uart_ocp_probe(device_t);
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static device_method_t uart_ocp_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, uart_ocp_probe),
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DEVMETHOD(device_attach, uart_bus_attach),
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DEVMETHOD(device_detach, uart_bus_detach),
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{ 0, 0 }
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};
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static driver_t uart_ocp_driver = {
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uart_driver_name,
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uart_ocp_methods,
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sizeof(struct uart_softc),
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};
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static int
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uart_ocp_probe(device_t dev)
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{
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device_t parent;
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struct uart_softc *sc;
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uintptr_t clock, devtype;
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int error;
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parent = device_get_parent(dev);
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error = BUS_READ_IVAR(parent, dev, OCPBUS_IVAR_DEVTYPE, &devtype);
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if (error)
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return (error);
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if (devtype != OCPBUS_DEVTYPE_UART)
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return (ENXIO);
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sc = device_get_softc(dev);
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sc->sc_class = &uart_ns8250_class;
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if (BUS_READ_IVAR(parent, dev, OCPBUS_IVAR_CLOCK, &clock))
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clock = 0;
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return (uart_bus_probe(dev, 0, clock, 0, 0));
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}
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DRIVER_MODULE(uart, ocpbus, uart_ocp_driver, uart_devclass, 0, 0);
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