453 lines
11 KiB
C
453 lines
11 KiB
C
/* $NecBSD: bshw.c,v 1.1 1997/07/18 09:19:03 kmatsuda Exp $ */
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/*
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* [NetBSD for NEC PC98 series]
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* Copyright (c) 1994, 1995, 1996 NetBSD/pc98 porting staff.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1994, 1995, 1996 Naofumi HONDA. All rights reserved.
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*
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* $FreeBSD$
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*/
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#ifdef __NetBSD__
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#include <dev/isa/isadmareg.h>
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#include <i386/Cbus/dev/bs/bsif.h>
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#include <i386/Cbus/dev/bs/bshw.lst>
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#endif
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#ifdef __FreeBSD__
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#include "opt_pc98.h"
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#include <i386/isa/ic/i8237.h>
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#include <i386/isa/bs/bsif.h>
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#include <i386/isa/bs/bshw.lst>
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#include <sys/cons.h>
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#endif
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static struct bs_softc *gbsc;
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/**************************************************
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* DECLARATION
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**************************************************/
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static void bshw_force_bsmode __P((struct bs_softc *));
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/**************************************************
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* STATIC VAL
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**************************************************/
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static int irq_tbl[] = { 3, 5, 6, 9, 12, 13 };
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/**************************************************
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* SCSI CMD BRANCH
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**************************************************/
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#define RS (BSSAT | BSSMIT | BSLINK | BSREAD)
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#define WS (BSSAT | BSSMIT | BSLINK)
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#define EOK (BSERROROK)
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u_int8_t bshw_cmd[256] = {
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/* 0 1 2 3 4 5 6 7 8 9 A B C E D F */
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/*0*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,RS ,0 ,WS ,0 ,0 ,0 ,0 ,0 ,
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/*1*/0 ,0 ,EOK,0 ,0 ,0 ,0 ,0 ,0 ,0 ,EOK,0 ,0 ,0 ,0 ,0 ,
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/*2*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,RS ,0 ,WS ,0 ,0 ,0 ,0 ,0 ,
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/*3*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*4*/0 ,0 ,EOK,EOK,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*5*/0 ,0 ,0 ,0 ,EOK,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*6*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*7*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*8*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*9*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*A*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*B*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*C*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*D*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*E*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*F*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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};
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#undef RS
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#undef WS
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#undef EOK
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/**********************************************
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* init
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**********************************************/
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static void
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bshw_force_bsmode(bsc)
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struct bs_softc *bsc;
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{
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if (bsc->sc_flags & BSBSMODE)
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return;
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bsc->sc_flags |= BSBSMODE;
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/*
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* If you have memory over 16M, some stupid boards always force to
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* use the io polling mode. Check such a case and change mode into
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* bus master DMA. However this depends heavily on the board's
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* specifications!
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*/
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if (bsc->sc_hw->dma_init && ((*bsc->sc_hw->dma_init)(bsc)))
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printf("%s change mode using external DMA (%x)\n",
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bsc->sc_dvname, (u_int)read_wd33c93(bsc, 0x37));
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}
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#define RESET_DEFAULT 2000
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int
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bshw_chip_reset(bsc)
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struct bs_softc *bsc;
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{
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int ct;
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u_int8_t aux;
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bshw_lock(bsc);
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bshw_abort_cmd(bsc);
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delay(10000);
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bshw_get_auxstat(bsc);
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bshw_get_busstat(bsc);
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write_wd33c93(bsc, wd3s_oid, IDR_EHP | bsc->sc_cspeed | bsc->sc_hostid);
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write_wd33c93(bsc, wd3s_cmd, WD3S_RESET);
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for (ct = RESET_DEFAULT; ct > 0; ct--)
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{
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aux = bshw_get_auxstat(bsc);
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if (aux != 0xff && (aux & STR_INT))
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{
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if (bshw_get_busstat(bsc) == 0)
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break;
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write_wd33c93(bsc, wd3s_cmd, WD3S_RESET);
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}
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delay(1);
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}
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if (ct == 0)
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{
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bshw_unlock(bsc);
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return ENXIO;
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}
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bshw_force_bsmode(bsc);
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write_wd33c93(bsc, wd3s_tout, BSHW_SEL_TIMEOUT);
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write_wd33c93(bsc, wd3s_sid, SIDR_RESEL);
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bsc->sc_flags |= BSDMATRANSFER;
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write_wd33c93(bsc, wd3s_ctrl, CR_DEFAULT);
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write_wd33c93(bsc, wd3s_synch, 0);
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bshw_get_auxstat(bsc);
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bsc->sc_busstat = bshw_get_busstat(bsc);
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bshw_unlock(bsc);
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return 0;
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}
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/* scsi bus hard reset */
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#define TWIDDLEWAIT 10000
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static int tw_pos;
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static char tw_chars[] = "|/-\\";
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/* this is some jokes */
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static void
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twiddle_wait(void)
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{
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cnputc('\b');
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cnputc(tw_chars[tw_pos++]);
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tw_pos %= (sizeof(tw_chars) - 1);
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delay(TWIDDLEWAIT);
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}
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static void bshw_set_vsp __P((struct bs_softc *, u_int, u_int8_t));
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static void
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bshw_set_vsp(bsc, chan, spva)
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struct bs_softc *bsc;
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u_int chan;
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u_int8_t spva;
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{
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struct bshw *hw = bsc->sc_hw;
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if (hw->sregaddr == 0)
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return;
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write_wd33c93(bsc, hw->sregaddr + chan, spva);
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if (hw->hw_flags & BSHW_DOUBLE_DMACHAN)
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write_wd33c93(bsc, hw->sregaddr + chan + 8, spva);
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}
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void
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bshw_bus_reset(bsc)
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struct bs_softc *bsc;
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{
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struct targ_info *ti;
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int i, lpc;
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if (bsc->sc_RSTdelay == 0)
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bsc->sc_RSTdelay = 6 * 1000 * 1000;
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else
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{
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/* XXX:
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* second time reset will be requested by hardware failuer.
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*/
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bsc->sc_RSTdelay = 12 * 1000 * 1000;
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}
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bshw_lock(bsc);
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write_wd33c93(bsc, wd3s_mbank, (bsc->sc_membank | MBR_RST) & ~MBR_IEN);
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delay(500000);
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write_wd33c93(bsc, wd3s_mbank, (bsc->sc_membank) & ~MBR_IEN);
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bshw_unlock(bsc);
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for (lpc = 0; lpc < 2; lpc ++)
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{
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cnputc(' ');
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for (i = 0; i <= bsc->sc_RSTdelay / TWIDDLEWAIT; i++)
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twiddle_wait();
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cnputc('\b');
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(void) read_wd33c93(bsc, wd3s_auxc);
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delay(10000);
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if ((read_wd33c93(bsc, wd3s_auxc) & AUXCR_RRST) == 0)
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break;
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printf("\nreset state still continue, wait ...");
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}
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for (i = 0; i < NTARGETS; i++)
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{
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if ((ti = bsc->sc_ti[i]) != NULL)
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{
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ti->ti_sync = 0;
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bshw_set_vsp(bsc, i, 0);
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}
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}
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}
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/* probe */
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int
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bshw_board_probe(bsc, drq, irq)
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struct bs_softc *bsc;
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u_int *drq;
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u_int *irq;
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{
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gbsc = bsc;
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#ifdef SHOW_PORT
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bshw_print_port(bsc);
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#endif /* SHOW_PORT */
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bsc->sc_hostid = (read_wd33c93(bsc, wd3s_auxc) & AUXCR_HIDM);
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if ((*irq) == IRQUNK)
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*irq = irq_tbl[(read_wd33c93(bsc, wd3s_auxc) >> 3) & 7];
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if ((*drq) == DRQUNK)
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*drq = BUS_IOR(cmd_port) & 3;
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bsc->sc_dmachan = *drq;
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bsc->sc_irq = (*irq);
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bsc->sc_membank = read_wd33c93(bsc, wd3s_mbank);
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bsc->sc_membank &= ~MBR_RST;
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bsc->sc_membank |= MBR_IEN;
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bsc->sc_cspeed = (read_wd33c93(bsc, wd3s_oid) & (~IDR_IDM));
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switch (BSC_CHIP_CLOCK(bsc->sc_cfgflags))
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{
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case 0:
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break;
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case 1:
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bsc->sc_cspeed &= ~(IDR_FS_12_15 | IDR_FS_15_20);
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break;
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case 2:
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bsc->sc_cspeed &= ~(IDR_FS_12_15 | IDR_FS_15_20);
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bsc->sc_cspeed |= IDR_FS_12_15;
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break;
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case 3:
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bsc->sc_cspeed &= ~(IDR_FS_12_15 | IDR_FS_15_20);
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bsc->sc_cspeed |= IDR_FS_15_20;
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break;
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}
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/* XXX: host id fixed(7) */
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bsc->sc_hostid = 7;
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if (bshw_chip_reset(bsc))
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return ENXIO;
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return 0;
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}
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/*
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* XXX:
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* Assume the board clock rate must be 20Mhz (always satisfied, maybe)!
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* Only 10M/s 6.6M/s 5.0M/s 3.3M/s for synchronus transfer speed set.
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*/
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#define ILLEGAL_SYNCH
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#ifdef ILLEGAL_SYNCH
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/* A 10 6.6 5.0 4.0 3.3 2.8 2.5 2.0 M/s */
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/* X 100 150 200 250 300 350 400 500 ns */
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static u_int bshw_scsi_period[] =
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{0, 25, 37, 50, 62, 75, 87, 100, 125};
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static u_int8_t bshw_chip_pval[] =
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{0, 0xa0, 0xb0, 0x20, 0xd0, 0x30, 0xf0, 0x40, 0x50};
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#else /* !ILLEGAL_SYNCH */
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/* A 10 6.6 5.0 3.3 2.5 M/s */
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/* X 100 150 200 300 400 ns */
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static u_int bshw_scsi_period[] =
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{0, 25, 37, 50, 75, 100};
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static u_int8_t bshw_chip_pval[] =
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{0, 0xa0, 0xb0, 0x20, 0x30, 0x40};
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#endif /* !ILLEGAL_SYNCH */
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void
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bshw_adj_syncdata(sdp)
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struct syncdata *sdp;
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{
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int i;
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if (sdp->offset == 0 || sdp->period < 25 || sdp->period > 100)
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sdp->offset = sdp->period = 0;
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else
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{
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for (i = 0; sdp->period > bshw_scsi_period[i] + 2; i ++)
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;
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sdp->period = bshw_scsi_period[i];
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}
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}
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void
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bshw_set_synchronous(bsc, ti)
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struct bs_softc *bsc;
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struct targ_info *ti;
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{
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struct syncdata sd;
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int i;
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sd = ti->ti_syncnow;
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bshw_adj_syncdata(&sd);
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for (i = 0; sd.period != bshw_scsi_period[i]; i++)
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;
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ti->ti_sync = ((sd.offset & 0x0f) | bshw_chip_pval[i]);
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bshw_set_vsp(bsc, ti->ti_id, ti->ti_sync);
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if (bsc->sc_nexus == ti)
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bshw_set_sync_reg(bsc, ti->ti_sync);
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}
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/* ctrl reg */
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void
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bshw_setup_ctrl_reg(bsc, flags)
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struct bs_softc *bsc;
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u_int flags;
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{
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u_int8_t regval;
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regval = (flags & BS_SCSI_NOPARITY) ? CR_DEFAULT : CR_DEFAULT_HP;
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if (bsc->sc_flags & BSDMATRANSFER)
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regval |= CR_DMA;
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write_wd33c93(bsc, wd3s_ctrl, regval);
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}
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/* sat command */
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void
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bshw_issue_satcmd(bsc, cb, link)
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struct bs_softc *bsc;
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struct bsccb *cb;
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int link;
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{
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int i;
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BUS_IOW(addr_port, wd3s_cdb);
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for (i = 0; i < cb->cmdlen - 1; i++)
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BUS_IOW(ctrl_port, cb->cmd[i]);
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BUS_IOW(ctrl_port, cb->cmd[i] | (link ? 1 : 0));
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}
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/* lock */
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void
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bshw_lock(bsc)
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struct bs_softc *bsc;
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{
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bsc->sc_hwlock++;
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write_wd33c93(bsc, wd3s_mbank, bsc->sc_membank & (~MBR_IEN));
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}
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void
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bshw_unlock(bsc)
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struct bs_softc *bsc;
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{
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if ((--bsc->sc_hwlock) <= 0)
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write_wd33c93(bsc, wd3s_mbank, bsc->sc_membank);
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}
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/**********************************************
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* DMA OPERATIONS
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**********************************************/
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#ifdef __NetBSD__
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#include <i386/Cbus/dev/bs/bshw_dma.c>
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#include <i386/Cbus/dev/bs/bshw_pdma.c>
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#endif
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#ifdef __FreeBSD__
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#include <i386/isa/bs/bshw_dma.c>
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#include <i386/isa/bs/bshw_pdma.c>
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#endif
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/**********************************************
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* DEBUG
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**********************************************/
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/* misc */
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void
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bshw_print_port(bsc)
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struct bs_softc * bsc;
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{
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int i, j;
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int port = 0x0;
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if (bsc == NULL)
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bsc = gbsc;
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printf("\n");
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for (j = 0; j <= 0x70; j += 0x10)
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{
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printf("port %x: ", port);
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for (i = 0; i < 0x10; i++)
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printf("%x ", (u_int) read_wd33c93(bsc, port++));
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printf("\n");
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}
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}
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