c31d0cf77b
its primary use is for the FEPS/FAS366 SCSI found in Sun Ultra 1e and 2 machines. Once the pci front-end is ported, this driver can replace the amd(4) driver. The code as-is is fairly stable. I've disabled tagged-queueing until I can figure out a corruption bug related to it. I'm importing it now so that people with these machines can (finally) stop netbooting and report bugs before 5.3.
723 lines
19 KiB
C
723 lines
19 KiB
C
/*-
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* Copyright (c) 2004 Scott Long
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/* $NetBSD: lsi64854.c,v 1.22 2002/10/01 07:07:03 petrov Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Kranenburg.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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|
* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/resource.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <machine/bus.h>
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#include <cam/cam.h>
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#include <cam/cam_ccb.h>
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#include <cam/scsi/scsi_all.h>
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#include <dev/esp/lsi64854reg.h>
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#include <dev/esp/lsi64854var.h>
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#include <dev/esp/ncr53c9xreg.h>
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#include <dev/esp/ncr53c9xvar.h>
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void lsi64854_reset(struct lsi64854_softc *);
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int lsi64854_setup(struct lsi64854_softc *, caddr_t *, size_t *,
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int, size_t *);
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int lsi64854_setup_pp(struct lsi64854_softc *, caddr_t *, size_t *,
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int, size_t *);
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#ifdef DEBUG
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#define LDB_SCSI 1
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#define LDB_ENET 2
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#define LDB_PP 4
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#define LDB_ANY 0xff
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int lsi64854debug = 0;
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#define DPRINTF(a,x) do { if (lsi64854debug & (a)) printf x ; } while (0)
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#else
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#define DPRINTF(a,x)
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#endif
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#define MAX_DMA_SZ (16*1024*1024)
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/*
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* Finish attaching this DMA device.
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* Front-end must fill in these fields:
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* sc_regs
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* sc_burst
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* sc_channel (one of SCSI, ENET, PP)
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* sc_client (one of SCSI, ENET, PP `soft_c' pointers)
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*/
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void
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lsi64854_attach(struct lsi64854_softc *sc)
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{
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u_int32_t csr;
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sc->dv_name = device_get_nameunit(sc->sc_dev);
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/* Indirect functions */
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switch (sc->sc_channel) {
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case L64854_CHANNEL_SCSI:
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sc->intr = lsi64854_scsi_intr;
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sc->setup = lsi64854_setup;
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break;
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case L64854_CHANNEL_ENET:
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sc->intr = lsi64854_enet_intr;
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break;
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case L64854_CHANNEL_PP:
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sc->setup = lsi64854_setup_pp;
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break;
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default:
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printf("%s: unknown channel\n", sc->dv_name);
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}
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sc->reset = lsi64854_reset;
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/* Allocate a dmamap */
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if (bus_dma_tag_create(sc->sc_parent_dmat, /* parent */
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1, 0, /* algnment, boundary */
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BUS_SPACE_MAXADDR, /* lowaddr */
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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MAX_DMA_SZ, /* maxsize */
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1, /* nsegments */
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MAX_DMA_SZ, /* maxsegsize */
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BUS_DMA_ALLOCNOW, /* flags */
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NULL, NULL, /* lockfunc, lockarg */
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&sc->sc_buffer_dmat)) {
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printf("%s: can't allocate buffer DMA tag\n", sc->dv_name);
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return;
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}
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if (bus_dmamap_create(sc->sc_buffer_dmat, 0, &sc->sc_dmamap) != 0) {
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printf("%s: DMA map create failed\n", sc->dv_name);
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return;
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}
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csr = L64854_GCSR(sc);
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sc->sc_rev = csr & L64854_DEVID;
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if (sc->sc_rev == DMAREV_HME) {
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return;
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}
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printf(": DMA rev ");
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switch (sc->sc_rev) {
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case DMAREV_0:
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printf("0");
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break;
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case DMAREV_ESC:
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printf("esc");
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break;
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case DMAREV_1:
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printf("1");
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break;
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case DMAREV_PLUS:
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printf("1+");
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break;
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case DMAREV_2:
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printf("2");
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break;
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default:
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printf("unknown (0x%x)", sc->sc_rev);
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}
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DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x", sc->sc_burst, csr));
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printf("\n");
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}
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/*
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* DMAWAIT waits while condition is true
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*/
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#define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \
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int count = 500000; \
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while ((COND) && --count > 0) DELAY(1); \
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if (count == 0) { \
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printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \
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(u_long)L64854_GCSR(SC)); \
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if (DONTPANIC) \
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printf(MSG); \
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else \
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panic(MSG); \
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} \
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} while (0)
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#define DMA_DRAIN(sc, dontpanic) do { \
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u_int32_t csr; \
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/* \
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* DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \
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* and "drain" bits while it is still thinking about a \
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* request. \
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* other revs: D_ESC_R_PEND bit reads as 0 \
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*/ \
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DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\
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if (sc->sc_rev != DMAREV_HME) { \
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/* \
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* Select drain bit based on revision \
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* also clears errors and D_TC flag \
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*/ \
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csr = L64854_GCSR(sc); \
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if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \
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csr |= D_ESC_DRAIN; \
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else \
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csr |= L64854_INVALIDATE; \
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\
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L64854_SCSR(sc,csr); \
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} \
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/* \
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* Wait for draining to finish \
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* rev0 & rev1 call this PACKCNT \
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*/ \
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DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\
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} while(0)
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#define DMA_FLUSH(sc, dontpanic) do { \
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u_int32_t csr; \
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/* \
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* DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \
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* and "drain" bits while it is still thinking about a \
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* request. \
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* other revs: D_ESC_R_PEND bit reads as 0 \
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*/ \
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DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\
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csr = L64854_GCSR(sc); \
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csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \
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csr |= L64854_INVALIDATE; /* XXX FAS ? */ \
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L64854_SCSR(sc,csr); \
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} while(0)
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void
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lsi64854_reset(struct lsi64854_softc *sc)
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{
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u_int32_t csr;
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DMA_FLUSH(sc, 1);
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csr = L64854_GCSR(sc);
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DPRINTF(LDB_ANY, ("lsi64854_reset: csr 0x%x\n", csr));
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/*
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* XXX is sync needed?
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if (sc->sc_dmamap->dm_nsegs > 0)
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bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap);
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*/
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if (sc->sc_rev == DMAREV_HME)
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L64854_SCSR(sc, csr | D_HW_RESET_FAS366);
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csr |= L64854_RESET; /* reset DMA */
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L64854_SCSR(sc, csr);
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DELAY(200); /* > 10 Sbus clocks(?) */
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/*DMAWAIT1(sc); why was this here? */
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csr = L64854_GCSR(sc);
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csr &= ~L64854_RESET; /* de-assert reset line */
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L64854_SCSR(sc, csr);
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DELAY(5); /* allow a few ticks to settle */
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csr = L64854_GCSR(sc);
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csr |= L64854_INT_EN; /* enable interrupts */
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if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI) {
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if (sc->sc_rev == DMAREV_HME)
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csr |= D_TWO_CYCLE;
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else
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csr |= D_FASTER;
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}
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/* Set burst */
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switch (sc->sc_rev) {
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case DMAREV_HME:
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case DMAREV_2:
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csr &= ~L64854_BURST_SIZE;
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if (sc->sc_burst == 32) {
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csr |= L64854_BURST_32;
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} else if (sc->sc_burst == 16) {
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csr |= L64854_BURST_16;
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} else {
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csr |= L64854_BURST_0;
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}
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break;
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case DMAREV_ESC:
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csr |= D_ESC_AUTODRAIN; /* Auto-drain */
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if (sc->sc_burst == 32) {
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csr &= ~D_ESC_BURST;
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} else
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csr |= D_ESC_BURST;
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break;
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default:
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break;
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}
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L64854_SCSR(sc, csr);
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if (sc->sc_rev == DMAREV_HME) {
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bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR, 0);
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sc->sc_dmactl = csr;
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}
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sc->sc_active = 0;
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DPRINTF(LDB_ANY, ("lsi64854_reset: done, csr 0x%x\n", csr));
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}
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static void
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lsi64854_map_scsi(void *arg, bus_dma_segment_t *segs, int nseg, int error)
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{
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struct lsi64854_softc *sc;
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sc = (struct lsi64854_softc *)arg;
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if (nseg != 1)
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panic("%s: cannot map %d segments\n", sc->dv_name, nseg);
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bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, sc->sc_datain ?
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BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
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bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR,
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segs[0].ds_addr);
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}
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|
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#define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1)))
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/*
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* setup a DMA transfer
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*/
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int
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lsi64854_setup(struct lsi64854_softc *sc, caddr_t *addr, size_t *len,
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int datain, size_t *dmasize)
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{
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u_int32_t csr;
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DMA_FLUSH(sc, 0);
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|
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#if 0
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DMACSR(sc) &= ~D_INT_EN;
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#endif
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sc->sc_dmaaddr = addr;
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sc->sc_dmalen = len;
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sc->sc_datain = datain;
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|
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/*
|
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* the rules say we cannot transfer more than the limit
|
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* of this DMA chip (64k for old and 16Mb for new),
|
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* and we cannot cross a 16Mb boundary.
|
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*/
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*dmasize = sc->sc_dmasize =
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min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr));
|
|
|
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DPRINTF(LDB_ANY, ("dma_setup: dmasize = %ld\n", (long)sc->sc_dmasize));
|
|
|
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/*
|
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* XXX what length?
|
|
*/
|
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if (sc->sc_rev == DMAREV_HME) {
|
|
|
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L64854_SCSR(sc, sc->sc_dmactl | L64854_RESET);
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L64854_SCSR(sc, sc->sc_dmactl);
|
|
|
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bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_CNT, *dmasize);
|
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}
|
|
|
|
/* Program the DMA address */
|
|
if (sc->sc_dmasize) {
|
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if (bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap,
|
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*sc->sc_dmaaddr, sc->sc_dmasize,
|
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lsi64854_map_scsi, sc, 0) != 0)
|
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panic("%s: cannot allocate DVMA address", sc->dv_name);
|
|
}
|
|
|
|
if (sc->sc_rev == DMAREV_ESC) {
|
|
/* DMA ESC chip bug work-around */
|
|
long bcnt = sc->sc_dmasize;
|
|
long eaddr = bcnt + (long)*sc->sc_dmaaddr;
|
|
if ((eaddr & PAGE_MASK_8K) != 0)
|
|
bcnt = roundup(bcnt, PAGE_SIZE_8K);
|
|
bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_CNT,
|
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bcnt);
|
|
}
|
|
|
|
/* Setup DMA control register */
|
|
csr = L64854_GCSR(sc);
|
|
|
|
if (datain)
|
|
csr |= L64854_WRITE;
|
|
else
|
|
csr &= ~L64854_WRITE;
|
|
csr |= L64854_INT_EN;
|
|
|
|
if (sc->sc_rev == DMAREV_HME) {
|
|
csr |= (D_DSBL_SCSI_DRN | D_EN_DMA);
|
|
}
|
|
|
|
L64854_SCSR(sc, csr);
|
|
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* Pseudo (chained) interrupt from the esp driver to kick the
|
|
* current running DMA transfer. Called from ncr53c9x_intr()
|
|
* for now.
|
|
*
|
|
* return 1 if it was a DMA continue.
|
|
*/
|
|
int
|
|
lsi64854_scsi_intr(void *arg)
|
|
{
|
|
struct lsi64854_softc *sc = arg;
|
|
struct ncr53c9x_softc *nsc = sc->sc_client;
|
|
int trans, resid;
|
|
u_int32_t csr;
|
|
|
|
csr = L64854_GCSR(sc);
|
|
|
|
DPRINTF(LDB_SCSI, ("%s: dmaintr: addr 0x%x, csr %b\n", sc->dv_name,
|
|
bus_space_read_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR),
|
|
csr, DDMACSR_BITS));
|
|
|
|
if (csr & (D_ERR_PEND|D_SLAVE_ERR)) {
|
|
printf("%s: error: csr=%b\n", sc->dv_name, csr, DDMACSR_BITS);
|
|
csr &= ~D_EN_DMA; /* Stop DMA */
|
|
/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
|
|
csr |= D_INVALIDATE|D_SLAVE_ERR;
|
|
L64854_SCSR(sc, csr);
|
|
return (-1);
|
|
}
|
|
|
|
/* This is an "assertion" :) */
|
|
if (sc->sc_active == 0)
|
|
panic("dmaintr: DMA wasn't active");
|
|
|
|
DMA_DRAIN(sc, 0);
|
|
|
|
/* DMA has stopped */
|
|
csr &= ~D_EN_DMA;
|
|
L64854_SCSR(sc, csr);
|
|
sc->sc_active = 0;
|
|
|
|
if (sc->sc_dmasize == 0) {
|
|
/* A "Transfer Pad" operation completed */
|
|
DPRINTF(LDB_SCSI, ("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n",
|
|
NCR_READ_REG(nsc, NCR_TCL) |
|
|
(NCR_READ_REG(nsc, NCR_TCM) << 8),
|
|
NCR_READ_REG(nsc, NCR_TCL),
|
|
NCR_READ_REG(nsc, NCR_TCM)));
|
|
return 0;
|
|
}
|
|
|
|
resid = 0;
|
|
/*
|
|
* If a transfer onto the SCSI bus gets interrupted by the device
|
|
* (e.g. for a SAVEPOINTER message), the data in the FIFO counts
|
|
* as residual since the NCR53C9X counter registers get decremented
|
|
* as bytes are clocked into the FIFO.
|
|
*/
|
|
if (!(csr & D_WRITE) &&
|
|
(resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
|
|
DPRINTF(LDB_SCSI, ("dmaintr: empty esp FIFO of %d ", resid));
|
|
if (nsc->sc_rev == NCR_VARIANT_FAS366 &&
|
|
(NCR_READ_REG(nsc, NCR_CFG3) & NCRFASCFG3_EWIDE))
|
|
resid <<= 1;
|
|
}
|
|
|
|
if ((nsc->sc_espstat & NCRSTAT_TC) == 0) {
|
|
/*
|
|
* `Terminal count' is off, so read the residue
|
|
* out of the NCR53C9X counter registers.
|
|
*/
|
|
resid += (NCR_READ_REG(nsc, NCR_TCL) |
|
|
(NCR_READ_REG(nsc, NCR_TCM) << 8) |
|
|
((nsc->sc_cfg2 & NCRCFG2_FE)
|
|
? (NCR_READ_REG(nsc, NCR_TCH) << 16)
|
|
: 0));
|
|
|
|
if (resid == 0 && sc->sc_dmasize == 65536 &&
|
|
(nsc->sc_cfg2 & NCRCFG2_FE) == 0)
|
|
/* A transfer of 64K is encoded as `TCL=TCM=0' */
|
|
resid = 65536;
|
|
}
|
|
|
|
trans = sc->sc_dmasize - resid;
|
|
if (trans < 0) { /* transferred < 0 ? */
|
|
#if 0
|
|
/*
|
|
* This situation can happen in perfectly normal operation
|
|
* if the ESP is reselected while using DMA to select
|
|
* another target. As such, don't print the warning.
|
|
*/
|
|
printf("%s: xfer (%d) > req (%d)\n", sc->dv_name, trans,
|
|
sc->sc_dmasize);
|
|
#endif
|
|
trans = sc->sc_dmasize;
|
|
}
|
|
|
|
DPRINTF(LDB_SCSI, ("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
|
|
NCR_READ_REG(nsc, NCR_TCL),
|
|
NCR_READ_REG(nsc, NCR_TCM),
|
|
(nsc->sc_cfg2 & NCRCFG2_FE)
|
|
? NCR_READ_REG(nsc, NCR_TCH) : 0,
|
|
trans, resid));
|
|
|
|
#if 0 /* XXX */
|
|
if (sc->sc_dmamap->dm_nsegs > 0) {
|
|
bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap,
|
|
(csr & D_WRITE) != 0
|
|
? BUS_DMASYNC_POSTREAD
|
|
: BUS_DMASYNC_POSTWRITE);
|
|
bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap);
|
|
}
|
|
#endif
|
|
|
|
*sc->sc_dmalen -= trans;
|
|
*sc->sc_dmaaddr += trans;
|
|
|
|
#if 0 /* this is not normal operation just yet */
|
|
if (*sc->sc_dmalen == 0 ||
|
|
nsc->sc_phase != nsc->sc_prevphase)
|
|
return 0;
|
|
|
|
/* and again */
|
|
dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE);
|
|
return 1;
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Pseudo (chained) interrupt to le driver to handle DMA errors.
|
|
*/
|
|
int
|
|
lsi64854_enet_intr(void *arg)
|
|
{
|
|
struct lsi64854_softc *sc = arg;
|
|
u_int32_t csr;
|
|
static int dodrain = 0;
|
|
int rv;
|
|
|
|
csr = L64854_GCSR(sc);
|
|
|
|
/* If the DMA logic shows an interrupt, claim it */
|
|
rv = ((csr & E_INT_PEND) != 0) ? 1 : 0;
|
|
|
|
if (csr & (E_ERR_PEND|E_SLAVE_ERR)) {
|
|
printf("%s: error: csr=%b\n", sc->dv_name, csr, EDMACSR_BITS);
|
|
csr &= ~L64854_EN_DMA; /* Stop DMA */
|
|
/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
|
|
csr |= E_INVALIDATE|E_SLAVE_ERR;
|
|
L64854_SCSR(sc, csr);
|
|
DMA_RESET(sc);
|
|
dodrain = 1;
|
|
return (1);
|
|
}
|
|
|
|
if (dodrain) { /* XXX - is this necessary with D_DSBL_WRINVAL on? */
|
|
int i = 10;
|
|
csr |= E_DRAIN;
|
|
L64854_SCSR(sc, csr);
|
|
while (i-- > 0 && (L64854_GCSR(sc) & D_DRAINING))
|
|
DELAY(1);
|
|
}
|
|
|
|
return (rv | (*sc->sc_intrchain)(sc->sc_intrchainarg));
|
|
}
|
|
|
|
static void
|
|
lsi64854_map_pp(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
|
|
{
|
|
struct lsi64854_softc *sc;
|
|
|
|
sc = (struct lsi64854_softc *)arg;
|
|
|
|
if (nsegs != 1)
|
|
panic("%s: cannot map %d segments\n", sc->dv_name, nsegs);
|
|
|
|
bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, sc->sc_datain
|
|
? BUS_DMASYNC_PREREAD
|
|
: BUS_DMASYNC_PREWRITE);
|
|
bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR,
|
|
segs[0].ds_addr);
|
|
|
|
bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_CNT,
|
|
sc->sc_dmasize);
|
|
}
|
|
|
|
/*
|
|
* setup a DMA transfer
|
|
*/
|
|
int
|
|
lsi64854_setup_pp(struct lsi64854_softc *sc, caddr_t *addr, size_t *len,
|
|
int datain, size_t *dmasize)
|
|
{
|
|
u_int32_t csr;
|
|
|
|
DMA_FLUSH(sc, 0);
|
|
|
|
sc->sc_dmaaddr = addr;
|
|
sc->sc_dmalen = len;
|
|
sc->sc_datain = datain;
|
|
|
|
DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", sc->dv_name,
|
|
(long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0));
|
|
|
|
/*
|
|
* the rules say we cannot transfer more than the limit
|
|
* of this DMA chip (64k for old and 16Mb for new),
|
|
* and we cannot cross a 16Mb boundary.
|
|
*/
|
|
*dmasize = sc->sc_dmasize =
|
|
min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr));
|
|
|
|
DPRINTF(LDB_PP, ("dma_setup_pp: dmasize = %ld\n", (long)sc->sc_dmasize));
|
|
|
|
/* Program the DMA address */
|
|
if (sc->sc_dmasize) {
|
|
if (bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap,
|
|
*sc->sc_dmaaddr, sc->sc_dmasize,
|
|
lsi64854_map_pp, sc, 0) != 0)
|
|
panic("%s: pp cannot allocate DVMA address",
|
|
sc->dv_name);
|
|
}
|
|
|
|
/* Setup DMA control register */
|
|
csr = L64854_GCSR(sc);
|
|
csr &= ~L64854_BURST_SIZE;
|
|
if (sc->sc_burst == 32) {
|
|
csr |= L64854_BURST_32;
|
|
} else if (sc->sc_burst == 16) {
|
|
csr |= L64854_BURST_16;
|
|
} else {
|
|
csr |= L64854_BURST_0;
|
|
}
|
|
csr |= P_EN_DMA|P_INT_EN|P_EN_CNT;
|
|
#if 0
|
|
/* This bit is read-only in PP csr register */
|
|
if (datain)
|
|
csr |= P_WRITE;
|
|
else
|
|
csr &= ~P_WRITE;
|
|
#endif
|
|
L64854_SCSR(sc, csr);
|
|
|
|
return (0);
|
|
}
|
|
/*
|
|
* Parallel port DMA interrupt.
|
|
*/
|
|
int
|
|
lsi64854_pp_intr(void *arg)
|
|
{
|
|
struct lsi64854_softc *sc = arg;
|
|
int ret, trans, resid = 0;
|
|
u_int32_t csr;
|
|
|
|
csr = L64854_GCSR(sc);
|
|
|
|
DPRINTF(LDB_PP, ("%s: pp intr: addr 0x%x, csr %b\n", sc->dv_name,
|
|
bus_space_read_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR),
|
|
csr, PDMACSR_BITS));
|
|
|
|
if (csr & (P_ERR_PEND|P_SLAVE_ERR)) {
|
|
resid = bus_space_read_4(sc->sc_regt, sc->sc_regh,
|
|
L64854_REG_CNT);
|
|
printf("%s: pp error: resid %d csr=%b\n", sc->dv_name, resid,
|
|
csr, PDMACSR_BITS);
|
|
csr &= ~P_EN_DMA; /* Stop DMA */
|
|
/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
|
|
csr |= P_INVALIDATE|P_SLAVE_ERR;
|
|
L64854_SCSR(sc, csr);
|
|
return (1);
|
|
}
|
|
|
|
ret = (csr & P_INT_PEND) != 0;
|
|
|
|
if (sc->sc_active != 0) {
|
|
DMA_DRAIN(sc, 0);
|
|
resid = bus_space_read_4(sc->sc_regt, sc->sc_regh,
|
|
L64854_REG_CNT);
|
|
}
|
|
|
|
/* DMA has stopped */
|
|
csr &= ~D_EN_DMA;
|
|
L64854_SCSR(sc, csr);
|
|
sc->sc_active = 0;
|
|
|
|
trans = sc->sc_dmasize - resid;
|
|
if (trans < 0) { /* transferred < 0 ? */
|
|
trans = sc->sc_dmasize;
|
|
}
|
|
*sc->sc_dmalen -= trans;
|
|
*sc->sc_dmaaddr += trans;
|
|
|
|
#if 0 /* XXX */
|
|
if (sc->sc_dmamap->dm_nsegs > 0) {
|
|
bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap,
|
|
(csr & D_WRITE) != 0
|
|
? BUS_DMASYNC_POSTREAD
|
|
: BUS_DMASYNC_POSTWRITE);
|
|
bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap);
|
|
}
|
|
#endif
|
|
|
|
return (ret != 0);
|
|
}
|