1624 lines
78 KiB
C
1624 lines
78 KiB
C
/* $FreeBSD$ */
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/*
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* Copyright (c) 2000, 2001 by LSI Logic Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*
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* Name: MPI_CNFG.H
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* Title: MPI Config message, structures, and Pages
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* Creation Date: July 27, 2000
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*
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* MPI_CNFG.H Version: 01.02.11
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*
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* Version History
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* ---------------
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*
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* Date Version Description
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* -------- -------- ------------------------------------------------------
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* 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000.
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* 06-06-00 01.00.01 Update version number for 1.0 release.
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* 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages.
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* Added FcPhLowestVersion, FcPhHighestVersion, Reserved2
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* fields to FC_DEVICE_0 page, updated the page version.
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* Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in
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* SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages
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* and updated the page versions.
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* Added _RESPONSE_ID_MASK definition to SCSI_PORT_1
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* page and updated the page version.
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* Added Information field and _INFO_PARAMS_NEGOTIATED
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* definitionto SCSI_DEVICE_0 page.
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* 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the
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* page version.
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* Added BucketsRemaining to LAN_1 page, redefined the
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* state values, and updated the page version.
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* Revised bus width definitions in SCSI_PORT_0,
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* SCSI_DEVICE_0 and SCSI_DEVICE_1 pages.
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* 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page
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* version.
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* Moved FC_DEVICE_0 PageAddress description to spec.
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* 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field
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* widths in IOC_0 page and updated the page version.
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* 11-02-00 01.01.01 Original release for post 1.0 work
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* Added Manufacturing pages, IO Unit Page 2, SCSI SPI
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* Port Page 2, FC Port Page 4, FC Port Page 5
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* 11-15-00 01.01.02 Interim changes to match proposals
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* 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01.
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* 12-05-00 01.01.04 Modified config page actions.
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* 01-09-01 01.01.05 Added defines for page address formats.
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* Data size for Manufacturing pages 2 and 3 no longer
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* defined here.
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* Io Unit Page 2 size is fixed at 4 adapters and some
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* flags were changed.
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* SCSI Port Page 2 Device Settings modified.
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* New fields added to FC Port Page 0 and some flags
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* cleaned up.
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* Removed impedance flash from FC Port Page 1.
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* Added FC Port pages 6 and 7.
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* 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0.
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* 01-29-01 01.01.07 Changed some defines to make them 32 character unique.
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* Added some LinkType defines for FcPortPage0.
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* 02-20-01 01.01.08 Started using MPI_POINTER.
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* 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with
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* MPI_CONFIG_PAGETYPE_RAID_VOLUME.
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* Added definitions and structures for IOC Page 2 and
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* RAID Volume Page 2.
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* 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9.
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* CONFIG_PAGE_FC_PORT_3 now supports persistent by DID.
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* Added VendorId and ProductRevLevel fields to
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* RAIDVOL2_IM_PHYS_ID struct.
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* Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_
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* defines to make them compatible to MPI version 1.0.
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* Added structure offset comments.
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* 04-09-01 01.01.11 Added some new defines for the PageAddress field and
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* removed some obsolete ones.
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* Added IO Unit Page 3.
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* Modified defines for Scsi Port Page 2.
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* Modified RAID Volume Pages.
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* 08-08-01 01.02.01 Original release for v1.2 work.
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* Added SepID and SepBus to RVP2 IMPhysicalDisk struct.
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* Added defines for the SEP bits in RVP2 VolumeSettings.
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* Modified the DeviceSettings field in RVP2 to use the
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* proper structure.
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* Added defines for SES, SAF-TE, and cross channel for
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* IOCPage2 CapabilitiesFlags.
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* Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE.
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* Removed define for
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* MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE.
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* Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT.
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* 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035.
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* Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY
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* and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY.
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* Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS,
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* MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and
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* MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and
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* MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED.
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* Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED
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* and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED.
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* Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1.
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* Added rejected bits to SCSI Device Page 0 Information.
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* Increased size of ALPA array in FC Port Page 2 by one
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* and removed a one byte reserved field.
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* 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in
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* CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering.
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* Added structures for Manufacturing Page 4, IO Unit
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* Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and
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* RAID PhysDisk Page 0.
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* 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK.
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* Modified some of the new defines to make them 32
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* character unique.
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* Modified how variable length pages (arrays) are defined.
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* Added generic defines for hot spare pools and RAID
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* volume types.
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* 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR.
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* 03-14-02 01.02.06 Added PCISlotNum field to CONFIG_PAGE_IOC_1 along with
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* related define, and bumped the page version define.
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* 05-31-02 01.02.07 Added a Flags field to CONFIG_PAGE_IOC_2_RAID_VOL in a
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* reserved byte and added a define.
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* Added define for
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* MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE.
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* Added new config page: CONFIG_PAGE_IOC_5.
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* Added MaxAliases, MaxHardAliases, and NumCurrentAliases
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* fields to CONFIG_PAGE_FC_PORT_0.
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* Added AltConnector and NumRequestedAliases fields to
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* CONFIG_PAGE_FC_PORT_1.
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* Added new config page: CONFIG_PAGE_FC_PORT_10.
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* 07-12-02 01.02.08 Added more MPI_MANUFACTPAGE_DEVID_ defines.
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* Added additional MPI_SCSIDEVPAGE0_NP_ defines.
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* Added more MPI_SCSIDEVPAGE1_RP_ defines.
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* Added define for
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* MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE.
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* Added new config page: CONFIG_PAGE_SCSI_DEVICE_3.
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* Modified MPI_FCPORTPAGE5_FLAGS_ defines.
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* 09-16-02 01.02.09 Added MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG define.
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* 11-15-02 01.02.10 Added ConnectedID defines for CONFIG_PAGE_SCSI_PORT_0.
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* Added more Flags defines for CONFIG_PAGE_FC_PORT_1.
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* Added more Flags defines for CONFIG_PAGE_FC_DEVICE_0.
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* 04-01-03 01.02.11 Added RR_TOV field and additional Flags defines for
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* CONFIG_PAGE_FC_PORT_1.
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* Added define MPI_FCPORTPAGE5_FLAGS_DISABLE to disable
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* an alias.
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* Added more device id defines.
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* --------------------------------------------------------------------------
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*/
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#ifndef MPI_CNFG_H
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#define MPI_CNFG_H
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/*****************************************************************************
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*
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* C o n f i g M e s s a g e a n d S t r u c t u r e s
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*
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*****************************************************************************/
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typedef struct _CONFIG_PAGE_HEADER
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{
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U8 PageVersion; /* 00h */
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U8 PageLength; /* 01h */
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U8 PageNumber; /* 02h */
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U8 PageType; /* 03h */
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} CONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER,
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ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t;
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typedef union _CONFIG_PAGE_HEADER_UNION
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{
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ConfigPageHeader_t Struct;
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U8 Bytes[4];
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U16 Word16[2];
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U32 Word32;
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} ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion,
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CONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION;
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/****************************************************************************
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* PageType field values
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****************************************************************************/
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#define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00)
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#define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10)
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#define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20)
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#define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30)
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#define MPI_CONFIG_PAGEATTR_MASK (0xF0)
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#define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00)
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#define MPI_CONFIG_PAGETYPE_IOC (0x01)
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#define MPI_CONFIG_PAGETYPE_BIOS (0x02)
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#define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03)
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#define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04)
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#define MPI_CONFIG_PAGETYPE_FC_PORT (0x05)
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#define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06)
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#define MPI_CONFIG_PAGETYPE_LAN (0x07)
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#define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
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#define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09)
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#define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
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#define MPI_CONFIG_PAGETYPE_MASK (0x0F)
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#define MPI_CONFIG_TYPENUM_MASK (0x0FFF)
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/****************************************************************************
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* PageAddress field values
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****************************************************************************/
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#define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF)
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#define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF)
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#define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0)
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#define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00)
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#define MPI_SCSI_DEVICE_BUS_SHIFT (8)
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#define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000)
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#define MPI_FC_PORT_PGAD_PORT_SHIFT (28)
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#define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000)
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#define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000)
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#define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF)
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#define MPI_FC_PORT_PGAD_INDEX_SHIFT (0)
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#define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000)
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#define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28)
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#define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000)
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#define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000)
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#define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000)
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#define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28)
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#define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF)
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#define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0)
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#define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000)
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#define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00)
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#define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8)
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#define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF)
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#define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0)
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#define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
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#define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0)
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/****************************************************************************
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* Config Request Message
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****************************************************************************/
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typedef struct _MSG_CONFIG
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{
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U8 Action; /* 00h */
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U8 Reserved; /* 01h */
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U8 ChainOffset; /* 02h */
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U8 Function; /* 03h */
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U8 Reserved1[3]; /* 04h */
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U8 MsgFlags; /* 07h */
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U32 MsgContext; /* 08h */
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U8 Reserved2[8]; /* 0Ch */
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CONFIG_PAGE_HEADER Header; /* 14h */
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U32 PageAddress; /* 18h */
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SGE_IO_UNION PageBufferSGE; /* 1Ch */
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} MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG,
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Config_t, MPI_POINTER pConfig_t;
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/****************************************************************************
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* Action field values
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****************************************************************************/
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#define MPI_CONFIG_ACTION_PAGE_HEADER (0x00)
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#define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
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#define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
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#define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03)
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#define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
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#define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
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#define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
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/* Config Reply Message */
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typedef struct _MSG_CONFIG_REPLY
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{
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U8 Action; /* 00h */
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U8 Reserved; /* 01h */
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U8 MsgLength; /* 02h */
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U8 Function; /* 03h */
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U8 Reserved1[3]; /* 04h */
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U8 MsgFlags; /* 07h */
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U32 MsgContext; /* 08h */
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U8 Reserved2[2]; /* 0Ch */
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U16 IOCStatus; /* 0Eh */
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U32 IOCLogInfo; /* 10h */
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CONFIG_PAGE_HEADER Header; /* 14h */
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} MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY,
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ConfigReply_t, MPI_POINTER pConfigReply_t;
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/*****************************************************************************
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*
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* C o n f i g u r a t i o n P a g e s
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*
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*****************************************************************************/
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/****************************************************************************
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* Manufacturing Config pages
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****************************************************************************/
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#define MPI_MANUFACTPAGE_VENDORID_LSILOGIC (0x1000)
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#define MPI_MANUFACTPAGE_VENDORID_TREBIA (0x1783)
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#define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621)
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#define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624)
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#define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622)
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#define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628)
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#define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626)
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#define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030)
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#define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031)
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#define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032)
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#define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033)
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#define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040)
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#define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041)
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#define MPI_MANUFACTPAGE_DEVID_SA2010 (0x0804)
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#define MPI_MANUFACTPAGE_DEVID_SA2010ZC (0x0805)
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#define MPI_MANUFACTPAGE_DEVID_SA2020 (0x0806)
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#define MPI_MANUFACTPAGE_DEVID_SA2020ZC (0x0807)
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#define MPI_MANUFACTPAGE_DEVID_SNP1000 (0x0010)
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#define MPI_MANUFACTPAGE_DEVID_SNP500 (0x0020)
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typedef struct _CONFIG_PAGE_MANUFACTURING_0
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{
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CONFIG_PAGE_HEADER Header; /* 00h */
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U8 ChipName[16]; /* 04h */
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U8 ChipRevision[8]; /* 14h */
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U8 BoardName[16]; /* 1Ch */
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U8 BoardAssembly[16]; /* 2Ch */
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U8 BoardTracerNumber[16]; /* 3Ch */
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} CONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0,
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ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t;
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#define MPI_MANUFACTURING0_PAGEVERSION (0x00)
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typedef struct _CONFIG_PAGE_MANUFACTURING_1
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{
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CONFIG_PAGE_HEADER Header; /* 00h */
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U8 VPD[256]; /* 04h */
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} CONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1,
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ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t;
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#define MPI_MANUFACTURING1_PAGEVERSION (0x00)
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typedef struct _MPI_CHIP_REVISION_ID
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{
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U16 DeviceID; /* 00h */
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U8 PCIRevisionID; /* 02h */
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U8 Reserved; /* 03h */
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} MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID,
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MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t;
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/*
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* Host code (drivers, BIOS, utilities, etc.) should leave this define set to
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* one and check Header.PageLength at runtime.
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*/
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#ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS
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#define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
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#endif
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typedef struct _CONFIG_PAGE_MANUFACTURING_2
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{
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CONFIG_PAGE_HEADER Header; /* 00h */
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MPI_CHIP_REVISION_ID ChipId; /* 04h */
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U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */
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} CONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2,
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ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t;
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#define MPI_MANUFACTURING2_PAGEVERSION (0x00)
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/*
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* Host code (drivers, BIOS, utilities, etc.) should leave this define set to
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* one and check Header.PageLength at runtime.
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*/
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#ifndef MPI_MAN_PAGE_3_INFO_WORDS
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#define MPI_MAN_PAGE_3_INFO_WORDS (1)
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#endif
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typedef struct _CONFIG_PAGE_MANUFACTURING_3
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{
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CONFIG_PAGE_HEADER Header; /* 00h */
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MPI_CHIP_REVISION_ID ChipId; /* 04h */
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U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */
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} CONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3,
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|
ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t;
|
|
|
|
#define MPI_MANUFACTURING3_PAGEVERSION (0x00)
|
|
|
|
|
|
typedef struct _CONFIG_PAGE_MANUFACTURING_4
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U32 Reserved1; /* 04h */
|
|
U8 InfoOffset0; /* 08h */
|
|
U8 InfoSize0; /* 09h */
|
|
U8 InfoOffset1; /* 0Ah */
|
|
U8 InfoSize1; /* 0Bh */
|
|
U8 InquirySize; /* 0Ch */
|
|
U8 Reserved2; /* 0Dh */
|
|
U16 Reserved3; /* 0Eh */
|
|
U8 InquiryData[56]; /* 10h */
|
|
U32 ISVolumeSettings; /* 48h */
|
|
U32 IMEVolumeSettings; /* 4Ch */
|
|
U32 IMVolumeSettings; /* 50h */
|
|
} CONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4,
|
|
ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t;
|
|
|
|
#define MPI_MANUFACTURING4_PAGEVERSION (0x00)
|
|
|
|
|
|
/****************************************************************************
|
|
* IO Unit Config Pages
|
|
****************************************************************************/
|
|
|
|
typedef struct _CONFIG_PAGE_IO_UNIT_0
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U64 UniqueValue; /* 04h */
|
|
} CONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0,
|
|
IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t;
|
|
|
|
#define MPI_IOUNITPAGE0_PAGEVERSION (0x00)
|
|
|
|
|
|
typedef struct _CONFIG_PAGE_IO_UNIT_1
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U32 Flags; /* 04h */
|
|
} CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1,
|
|
IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t;
|
|
|
|
#define MPI_IOUNITPAGE1_PAGEVERSION (0x00)
|
|
|
|
/* IO Unit Page 1 Flags defines */
|
|
|
|
#define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000)
|
|
#define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001)
|
|
#define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002)
|
|
#define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000)
|
|
#define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040)
|
|
#define MPI_IOUNITPAGE1_FORCE_32 (0x00000080)
|
|
|
|
|
|
typedef struct _MPI_ADAPTER_INFO
|
|
{
|
|
U8 PciBusNumber; /* 00h */
|
|
U8 PciDeviceAndFunctionNumber; /* 01h */
|
|
U16 AdapterFlags; /* 02h */
|
|
} MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO,
|
|
MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t;
|
|
|
|
#define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
|
|
#define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
|
|
|
|
typedef struct _CONFIG_PAGE_IO_UNIT_2
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U32 Flags; /* 04h */
|
|
U32 BiosVersion; /* 08h */
|
|
MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */
|
|
} CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2,
|
|
IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t;
|
|
|
|
#define MPI_IOUNITPAGE2_PAGEVERSION (0x00)
|
|
|
|
#define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002)
|
|
#define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004)
|
|
#define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008)
|
|
#define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010)
|
|
|
|
|
|
/*
|
|
* Host code (drivers, BIOS, utilities, etc.) should leave this define set to
|
|
* one and check Header.PageLength at runtime.
|
|
*/
|
|
#ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX
|
|
#define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
|
|
#endif
|
|
|
|
typedef struct _CONFIG_PAGE_IO_UNIT_3
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U8 GPIOCount; /* 04h */
|
|
U8 Reserved1; /* 05h */
|
|
U16 Reserved2; /* 06h */
|
|
U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */
|
|
} CONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3,
|
|
IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t;
|
|
|
|
#define MPI_IOUNITPAGE3_PAGEVERSION (0x01)
|
|
|
|
#define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC)
|
|
#define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
|
|
#define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00)
|
|
#define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01)
|
|
|
|
|
|
/****************************************************************************
|
|
* IOC Config Pages
|
|
****************************************************************************/
|
|
|
|
typedef struct _CONFIG_PAGE_IOC_0
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U32 TotalNVStore; /* 04h */
|
|
U32 FreeNVStore; /* 08h */
|
|
U16 VendorID; /* 0Ch */
|
|
U16 DeviceID; /* 0Eh */
|
|
U8 RevisionID; /* 10h */
|
|
U8 Reserved[3]; /* 11h */
|
|
U32 ClassCode; /* 14h */
|
|
U16 SubsystemVendorID; /* 18h */
|
|
U16 SubsystemID; /* 1Ah */
|
|
} CONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0,
|
|
IOCPage0_t, MPI_POINTER pIOCPage0_t;
|
|
|
|
#define MPI_IOCPAGE0_PAGEVERSION (0x01)
|
|
|
|
|
|
typedef struct _CONFIG_PAGE_IOC_1
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U32 Flags; /* 04h */
|
|
U32 CoalescingTimeout; /* 08h */
|
|
U8 CoalescingDepth; /* 0Ch */
|
|
U8 PCISlotNum; /* 0Dh */
|
|
U8 Reserved[2]; /* 0Eh */
|
|
} CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1,
|
|
IOCPage1_t, MPI_POINTER pIOCPage1_t;
|
|
|
|
#define MPI_IOCPAGE1_PAGEVERSION (0x01)
|
|
|
|
#define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001)
|
|
|
|
#define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
|
|
|
|
|
|
typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL
|
|
{
|
|
U8 VolumeID; /* 00h */
|
|
U8 VolumeBus; /* 01h */
|
|
U8 VolumeIOC; /* 02h */
|
|
U8 VolumePageNumber; /* 03h */
|
|
U8 VolumeType; /* 04h */
|
|
U8 Flags; /* 05h */
|
|
U16 Reserved3; /* 06h */
|
|
} CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL,
|
|
ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t;
|
|
|
|
/* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */
|
|
|
|
#define MPI_RAID_VOL_TYPE_IS (0x00)
|
|
#define MPI_RAID_VOL_TYPE_IME (0x01)
|
|
#define MPI_RAID_VOL_TYPE_IM (0x02)
|
|
|
|
/* IOC Page 2 Volume Flags values */
|
|
|
|
#define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE (0x08)
|
|
|
|
/*
|
|
* Host code (drivers, BIOS, utilities, etc.) should leave this define set to
|
|
* one and check Header.PageLength at runtime.
|
|
*/
|
|
#ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX
|
|
#define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1)
|
|
#endif
|
|
|
|
typedef struct _CONFIG_PAGE_IOC_2
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U32 CapabilitiesFlags; /* 04h */
|
|
U8 NumActiveVolumes; /* 08h */
|
|
U8 MaxVolumes; /* 09h */
|
|
U8 NumActivePhysDisks; /* 0Ah */
|
|
U8 MaxPhysDisks; /* 0Bh */
|
|
CONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */
|
|
} CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2,
|
|
IOCPage2_t, MPI_POINTER pIOCPage2_t;
|
|
|
|
#define MPI_IOCPAGE2_PAGEVERSION (0x02)
|
|
|
|
/* IOC Page 2 Capabilities flags */
|
|
|
|
#define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001)
|
|
#define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002)
|
|
#define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004)
|
|
#define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000)
|
|
#define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000)
|
|
#define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000)
|
|
|
|
|
|
typedef struct _IOC_3_PHYS_DISK
|
|
{
|
|
U8 PhysDiskID; /* 00h */
|
|
U8 PhysDiskBus; /* 01h */
|
|
U8 PhysDiskIOC; /* 02h */
|
|
U8 PhysDiskNum; /* 03h */
|
|
} IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK,
|
|
Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t;
|
|
|
|
/*
|
|
* Host code (drivers, BIOS, utilities, etc.) should leave this define set to
|
|
* one and check Header.PageLength at runtime.
|
|
*/
|
|
#ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX
|
|
#define MPI_IOC_PAGE_3_PHYSDISK_MAX (1)
|
|
#endif
|
|
|
|
typedef struct _CONFIG_PAGE_IOC_3
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U8 NumPhysDisks; /* 04h */
|
|
U8 Reserved1; /* 05h */
|
|
U16 Reserved2; /* 06h */
|
|
IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */
|
|
} CONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3,
|
|
IOCPage3_t, MPI_POINTER pIOCPage3_t;
|
|
|
|
#define MPI_IOCPAGE3_PAGEVERSION (0x00)
|
|
|
|
|
|
typedef struct _IOC_4_SEP
|
|
{
|
|
U8 SEPTargetID; /* 00h */
|
|
U8 SEPBus; /* 01h */
|
|
U16 Reserved; /* 02h */
|
|
} IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP,
|
|
Ioc4Sep_t, MPI_POINTER pIoc4Sep_t;
|
|
|
|
/*
|
|
* Host code (drivers, BIOS, utilities, etc.) should leave this define set to
|
|
* one and check Header.PageLength at runtime.
|
|
*/
|
|
#ifndef MPI_IOC_PAGE_4_SEP_MAX
|
|
#define MPI_IOC_PAGE_4_SEP_MAX (1)
|
|
#endif
|
|
|
|
typedef struct _CONFIG_PAGE_IOC_4
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U8 ActiveSEP; /* 04h */
|
|
U8 MaxSEP; /* 05h */
|
|
U16 Reserved1; /* 06h */
|
|
IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */
|
|
} CONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4,
|
|
IOCPage4_t, MPI_POINTER pIOCPage4_t;
|
|
|
|
#define MPI_IOCPAGE4_PAGEVERSION (0x00)
|
|
|
|
|
|
typedef struct _IOC_5_HOT_SPARE
|
|
{
|
|
U8 PhysDiskNum; /* 00h */
|
|
U8 Reserved; /* 01h */
|
|
U8 HotSparePool; /* 02h */
|
|
U8 Flags; /* 03h */
|
|
} IOC_5_HOT_SPARE, MPI_POINTER PTR_IOC_5_HOT_SPARE,
|
|
Ioc5HotSpare_t, MPI_POINTER pIoc5HotSpare_t;
|
|
|
|
/* IOC Page 5 HotSpare Flags */
|
|
#define MPI_IOC_PAGE_5_HOT_SPARE_ACTIVE (0x01)
|
|
|
|
/*
|
|
* Host code (drivers, BIOS, utilities, etc.) should leave this define set to
|
|
* one and check Header.PageLength at runtime.
|
|
*/
|
|
#ifndef MPI_IOC_PAGE_5_HOT_SPARE_MAX
|
|
#define MPI_IOC_PAGE_5_HOT_SPARE_MAX (1)
|
|
#endif
|
|
|
|
typedef struct _CONFIG_PAGE_IOC_5
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U32 Reserved1; /* 04h */
|
|
U8 NumHotSpares; /* 08h */
|
|
U8 Reserved2; /* 09h */
|
|
U16 Reserved3; /* 0Ah */
|
|
IOC_5_HOT_SPARE HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */
|
|
} CONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5,
|
|
IOCPage5_t, MPI_POINTER pIOCPage5_t;
|
|
|
|
#define MPI_IOCPAGE5_PAGEVERSION (0x00)
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
* SCSI Port Config Pages
|
|
****************************************************************************/
|
|
|
|
typedef struct _CONFIG_PAGE_SCSI_PORT_0
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U32 Capabilities; /* 04h */
|
|
U32 PhysicalInterface; /* 08h */
|
|
} CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0,
|
|
SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t;
|
|
|
|
#define MPI_SCSIPORTPAGE0_PAGEVERSION (0x01)
|
|
|
|
#define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001)
|
|
#define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002)
|
|
#define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004)
|
|
#define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
|
|
#define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
|
|
#define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000)
|
|
#define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000)
|
|
|
|
#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003)
|
|
#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01)
|
|
#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02)
|
|
#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03)
|
|
#define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000)
|
|
#define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID (24)
|
|
#define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID (0xFE)
|
|
#define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID (0xFF)
|
|
|
|
|
|
typedef struct _CONFIG_PAGE_SCSI_PORT_1
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U32 Configuration; /* 04h */
|
|
U32 OnBusTimerValue; /* 08h */
|
|
} CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1,
|
|
SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t;
|
|
|
|
#define MPI_SCSIPORTPAGE1_PAGEVERSION (0x02)
|
|
|
|
#define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF)
|
|
#define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000)
|
|
|
|
|
|
typedef struct _MPI_DEVICE_INFO
|
|
{
|
|
U8 Timeout; /* 00h */
|
|
U8 SyncFactor; /* 01h */
|
|
U16 DeviceFlags; /* 02h */
|
|
} MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO,
|
|
MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t;
|
|
|
|
typedef struct _CONFIG_PAGE_SCSI_PORT_2
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U32 PortFlags; /* 04h */
|
|
U32 PortSettings; /* 08h */
|
|
MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */
|
|
} CONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2,
|
|
SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t;
|
|
|
|
#define MPI_SCSIPORTPAGE2_PAGEVERSION (0x01)
|
|
|
|
#define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001)
|
|
#define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004)
|
|
#define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008)
|
|
#define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010)
|
|
|
|
#define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F)
|
|
#define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030)
|
|
#define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000)
|
|
#define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010)
|
|
#define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020)
|
|
#define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030)
|
|
#define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0)
|
|
#define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00)
|
|
#define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000)
|
|
#define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000)
|
|
#define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000)
|
|
#define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000)
|
|
|
|
#define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001)
|
|
#define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002)
|
|
#define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004)
|
|
#define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008)
|
|
#define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010)
|
|
#define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020)
|
|
|
|
|
|
/****************************************************************************
|
|
* SCSI Target Device Config Pages
|
|
****************************************************************************/
|
|
|
|
typedef struct _CONFIG_PAGE_SCSI_DEVICE_0
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U32 NegotiatedParameters; /* 04h */
|
|
U32 Information; /* 08h */
|
|
} CONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0,
|
|
SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t;
|
|
|
|
#define MPI_SCSIDEVPAGE0_PAGEVERSION (0x03)
|
|
|
|
#define MPI_SCSIDEVPAGE0_NP_IU (0x00000001)
|
|
#define MPI_SCSIDEVPAGE0_NP_DT (0x00000002)
|
|
#define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004)
|
|
#define MPI_SCSIDEVPAGE0_NP_HOLD_MCS (0x00000008)
|
|
#define MPI_SCSIDEVPAGE0_NP_WR_FLOW (0x00000010)
|
|
#define MPI_SCSIDEVPAGE0_NP_RD_STRM (0x00000020)
|
|
#define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040)
|
|
#define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080)
|
|
#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00)
|
|
#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000)
|
|
#define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000)
|
|
#define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000)
|
|
|
|
#define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001)
|
|
#define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002)
|
|
#define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004)
|
|
#define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008)
|
|
|
|
|
|
typedef struct _CONFIG_PAGE_SCSI_DEVICE_1
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U32 RequestedParameters; /* 04h */
|
|
U32 Reserved; /* 08h */
|
|
U32 Configuration; /* 0Ch */
|
|
} CONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1,
|
|
SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t;
|
|
|
|
#define MPI_SCSIDEVPAGE1_PAGEVERSION (0x04)
|
|
|
|
#define MPI_SCSIDEVPAGE1_RP_IU (0x00000001)
|
|
#define MPI_SCSIDEVPAGE1_RP_DT (0x00000002)
|
|
#define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004)
|
|
#define MPI_SCSIDEVPAGE1_RP_HOLD_MCS (0x00000008)
|
|
#define MPI_SCSIDEVPAGE1_RP_WR_FLOW (0x00000010)
|
|
#define MPI_SCSIDEVPAGE1_RP_RD_STRM (0x00000020)
|
|
#define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040)
|
|
#define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080)
|
|
#define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
|
|
#define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
|
|
#define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000)
|
|
#define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000)
|
|
|
|
#define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002)
|
|
#define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004)
|
|
#define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE (0x00000008)
|
|
#define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG (0x00000010)
|
|
|
|
|
|
typedef struct _CONFIG_PAGE_SCSI_DEVICE_2
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U32 DomainValidation; /* 04h */
|
|
U32 ParityPipeSelect; /* 08h */
|
|
U32 DataPipeSelect; /* 0Ch */
|
|
} CONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2,
|
|
SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t;
|
|
|
|
#define MPI_SCSIDEVPAGE2_PAGEVERSION (0x01)
|
|
|
|
#define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010)
|
|
#define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020)
|
|
#define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380)
|
|
#define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00)
|
|
#define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000)
|
|
#define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000)
|
|
#define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000)
|
|
#define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000)
|
|
#define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000)
|
|
|
|
#define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003)
|
|
|
|
#define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003)
|
|
#define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C)
|
|
#define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030)
|
|
#define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0)
|
|
#define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300)
|
|
#define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00)
|
|
#define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000)
|
|
#define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000)
|
|
#define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000)
|
|
#define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000)
|
|
#define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000)
|
|
#define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000)
|
|
#define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000)
|
|
#define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000)
|
|
#define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000)
|
|
#define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000)
|
|
|
|
|
|
typedef struct _CONFIG_PAGE_SCSI_DEVICE_3
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U16 MsgRejectCount; /* 04h */
|
|
U16 PhaseErrorCount; /* 06h */
|
|
U16 ParityErrorCount; /* 08h */
|
|
U16 Reserved; /* 0Ah */
|
|
} CONFIG_PAGE_SCSI_DEVICE_3, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_3,
|
|
SCSIDevicePage3_t, MPI_POINTER pSCSIDevicePage3_t;
|
|
|
|
#define MPI_SCSIDEVPAGE3_PAGEVERSION (0x00)
|
|
|
|
#define MPI_SCSIDEVPAGE3_MAX_COUNTER (0xFFFE)
|
|
#define MPI_SCSIDEVPAGE3_UNSUPPORTED_COUNTER (0xFFFF)
|
|
|
|
|
|
/****************************************************************************
|
|
* FC Port Config Pages
|
|
****************************************************************************/
|
|
|
|
typedef struct _CONFIG_PAGE_FC_PORT_0
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U32 Flags; /* 04h */
|
|
U8 MPIPortNumber; /* 08h */
|
|
U8 LinkType; /* 09h */
|
|
U8 PortState; /* 0Ah */
|
|
U8 Reserved; /* 0Bh */
|
|
U32 PortIdentifier; /* 0Ch */
|
|
U64 WWNN; /* 10h */
|
|
U64 WWPN; /* 18h */
|
|
U32 SupportedServiceClass; /* 20h */
|
|
U32 SupportedSpeeds; /* 24h */
|
|
U32 CurrentSpeed; /* 28h */
|
|
U32 MaxFrameSize; /* 2Ch */
|
|
U64 FabricWWNN; /* 30h */
|
|
U64 FabricWWPN; /* 38h */
|
|
U32 DiscoveredPortsCount; /* 40h */
|
|
U32 MaxInitiators; /* 44h */
|
|
U8 MaxAliasesSupported; /* 48h */
|
|
U8 MaxHardAliasesSupported; /* 49h */
|
|
U8 NumCurrentAliases; /* 4Ah */
|
|
U8 Reserved1; /* 4Bh */
|
|
} CONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0,
|
|
FCPortPage0_t, MPI_POINTER pFCPortPage0_t;
|
|
|
|
#define MPI_FCPORTPAGE0_PAGEVERSION (0x02)
|
|
|
|
#define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F)
|
|
#define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR)
|
|
#define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET)
|
|
#define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN)
|
|
#define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR)
|
|
|
|
#define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010)
|
|
#define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020)
|
|
#define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000040)
|
|
|
|
#define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00)
|
|
#define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000)
|
|
#define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100)
|
|
#define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200)
|
|
#define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400)
|
|
#define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800)
|
|
|
|
#define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00)
|
|
#define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01)
|
|
#define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02)
|
|
#define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03)
|
|
#define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04)
|
|
#define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05)
|
|
#define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06)
|
|
#define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07)
|
|
#define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08)
|
|
#define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09)
|
|
#define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A)
|
|
#define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B)
|
|
#define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C)
|
|
#define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D)
|
|
#define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E)
|
|
#define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F)
|
|
|
|
#define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */
|
|
#define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */
|
|
#define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */
|
|
#define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */
|
|
#define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */
|
|
#define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */
|
|
#define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */
|
|
#define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */
|
|
|
|
#define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001)
|
|
#define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002)
|
|
#define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004)
|
|
|
|
#define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */
|
|
#define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */
|
|
#define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */
|
|
|
|
#define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED
|
|
#define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED
|
|
#define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED
|
|
|
|
|
|
typedef struct _CONFIG_PAGE_FC_PORT_1
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U32 Flags; /* 04h */
|
|
U64 NoSEEPROMWWNN; /* 08h */
|
|
U64 NoSEEPROMWWPN; /* 10h */
|
|
U8 HardALPA; /* 18h */
|
|
U8 LinkConfig; /* 19h */
|
|
U8 TopologyConfig; /* 1Ah */
|
|
U8 AltConnector; /* 1Bh */
|
|
U8 NumRequestedAliases; /* 1Ch */
|
|
U8 RR_TOV; /* 1Dh */
|
|
U16 Reserved2; /* 1Eh */
|
|
} CONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1,
|
|
FCPortPage1_t, MPI_POINTER pFCPortPage1_t;
|
|
|
|
#define MPI_FCPORTPAGE1_PAGEVERSION (0x05)
|
|
|
|
#define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000)
|
|
#define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000)
|
|
#define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS (0x02000000)
|
|
#define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS (0x01000000)
|
|
#define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID (0x00800000)
|
|
#define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS (0x00000070)
|
|
#define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS (0x00000002)
|
|
#define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001)
|
|
#define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000)
|
|
|
|
#define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000)
|
|
#define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28)
|
|
#define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
|
|
#define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
|
|
#define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
|
|
#define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
|
|
|
|
#define MPI_FCPORTPAGE1_FLAGS_NONE_RR_TOV_UNITS (0x00000000)
|
|
#define MPI_FCPORTPAGE1_FLAGS_THOUSANDTH_RR_TOV_UNITS (0x00000010)
|
|
#define MPI_FCPORTPAGE1_FLAGS_TENTH_RR_TOV_UNITS (0x00000030)
|
|
#define MPI_FCPORTPAGE1_FLAGS_TEN_RR_TOV_UNITS (0x00000050)
|
|
|
|
#define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF)
|
|
|
|
#define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F)
|
|
#define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00)
|
|
#define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01)
|
|
#define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02)
|
|
#define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03)
|
|
#define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F)
|
|
|
|
#define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F)
|
|
#define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01)
|
|
#define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02)
|
|
#define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F)
|
|
|
|
#define MPI_FCPORTPAGE1_ALT_CONN_UNKNOWN (0x00)
|
|
|
|
|
|
typedef struct _CONFIG_PAGE_FC_PORT_2
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U8 NumberActive; /* 04h */
|
|
U8 ALPA[127]; /* 05h */
|
|
} CONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2,
|
|
FCPortPage2_t, MPI_POINTER pFCPortPage2_t;
|
|
|
|
#define MPI_FCPORTPAGE2_PAGEVERSION (0x01)
|
|
|
|
|
|
typedef struct _WWN_FORMAT
|
|
{
|
|
U64 WWNN; /* 00h */
|
|
U64 WWPN; /* 08h */
|
|
} WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT,
|
|
WWNFormat, MPI_POINTER pWWNFormat;
|
|
|
|
typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID
|
|
{
|
|
WWN_FORMAT WWN;
|
|
U32 Did;
|
|
} FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID,
|
|
PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t;
|
|
|
|
typedef struct _FC_PORT_PERSISTENT
|
|
{
|
|
FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */
|
|
U8 TargetID; /* 10h */
|
|
U8 Bus; /* 11h */
|
|
U16 Flags; /* 12h */
|
|
} FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT,
|
|
PersistentData_t, MPI_POINTER pPersistentData_t;
|
|
|
|
#define MPI_PERSISTENT_FLAGS_SHIFT (16)
|
|
#define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001)
|
|
#define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002)
|
|
#define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004)
|
|
#define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008)
|
|
#define MPI_PERSISTENT_FLAGS_BY_DID (0x0080)
|
|
|
|
/*
|
|
* Host code (drivers, BIOS, utilities, etc.) should leave this define set to
|
|
* one and check Header.PageLength at runtime.
|
|
*/
|
|
#ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX
|
|
#define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1)
|
|
#endif
|
|
|
|
typedef struct _CONFIG_PAGE_FC_PORT_3
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */
|
|
} CONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3,
|
|
FCPortPage3_t, MPI_POINTER pFCPortPage3_t;
|
|
|
|
#define MPI_FCPORTPAGE3_PAGEVERSION (0x01)
|
|
|
|
|
|
typedef struct _CONFIG_PAGE_FC_PORT_4
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U32 PortFlags; /* 04h */
|
|
U32 PortSettings; /* 08h */
|
|
} CONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4,
|
|
FCPortPage4_t, MPI_POINTER pFCPortPage4_t;
|
|
|
|
#define MPI_FCPORTPAGE4_PAGEVERSION (0x00)
|
|
|
|
#define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008)
|
|
|
|
#define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030)
|
|
#define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000)
|
|
#define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010)
|
|
#define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020)
|
|
#define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030)
|
|
#define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0)
|
|
#define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00)
|
|
|
|
|
|
typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO
|
|
{
|
|
U8 Flags; /* 00h */
|
|
U8 AliasAlpa; /* 01h */
|
|
U16 Reserved; /* 02h */
|
|
U64 AliasWWNN; /* 04h */
|
|
U64 AliasWWPN; /* 0Ch */
|
|
} CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
|
|
MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
|
|
FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t;
|
|
|
|
typedef struct _CONFIG_PAGE_FC_PORT_5
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
CONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo; /* 04h */
|
|
} CONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5,
|
|
FCPortPage5_t, MPI_POINTER pFCPortPage5_t;
|
|
|
|
#define MPI_FCPORTPAGE5_PAGEVERSION (0x02)
|
|
|
|
#define MPI_FCPORTPAGE5_FLAGS_ALPA_ACQUIRED (0x01)
|
|
#define MPI_FCPORTPAGE5_FLAGS_HARD_ALPA (0x02)
|
|
#define MPI_FCPORTPAGE5_FLAGS_HARD_WWNN (0x04)
|
|
#define MPI_FCPORTPAGE5_FLAGS_HARD_WWPN (0x08)
|
|
#define MPI_FCPORTPAGE5_FLAGS_DISABLE (0x10)
|
|
|
|
typedef struct _CONFIG_PAGE_FC_PORT_6
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U32 Reserved; /* 04h */
|
|
U64 TimeSinceReset; /* 08h */
|
|
U64 TxFrames; /* 10h */
|
|
U64 RxFrames; /* 18h */
|
|
U64 TxWords; /* 20h */
|
|
U64 RxWords; /* 28h */
|
|
U64 LipCount; /* 30h */
|
|
U64 NosCount; /* 38h */
|
|
U64 ErrorFrames; /* 40h */
|
|
U64 DumpedFrames; /* 48h */
|
|
U64 LinkFailureCount; /* 50h */
|
|
U64 LossOfSyncCount; /* 58h */
|
|
U64 LossOfSignalCount; /* 60h */
|
|
U64 PrimativeSeqErrCount; /* 68h */
|
|
U64 InvalidTxWordCount; /* 70h */
|
|
U64 InvalidCrcCount; /* 78h */
|
|
U64 FcpInitiatorIoCount; /* 80h */
|
|
} CONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6,
|
|
FCPortPage6_t, MPI_POINTER pFCPortPage6_t;
|
|
|
|
#define MPI_FCPORTPAGE6_PAGEVERSION (0x00)
|
|
|
|
|
|
typedef struct _CONFIG_PAGE_FC_PORT_7
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U32 Reserved; /* 04h */
|
|
U8 PortSymbolicName[256]; /* 08h */
|
|
} CONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7,
|
|
FCPortPage7_t, MPI_POINTER pFCPortPage7_t;
|
|
|
|
#define MPI_FCPORTPAGE7_PAGEVERSION (0x00)
|
|
|
|
|
|
typedef struct _CONFIG_PAGE_FC_PORT_8
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U32 BitVector[8]; /* 04h */
|
|
} CONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8,
|
|
FCPortPage8_t, MPI_POINTER pFCPortPage8_t;
|
|
|
|
#define MPI_FCPORTPAGE8_PAGEVERSION (0x00)
|
|
|
|
|
|
typedef struct _CONFIG_PAGE_FC_PORT_9
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U32 Reserved; /* 04h */
|
|
U64 GlobalWWPN; /* 08h */
|
|
U64 GlobalWWNN; /* 10h */
|
|
U32 UnitType; /* 18h */
|
|
U32 PhysicalPortNumber; /* 1Ch */
|
|
U32 NumAttachedNodes; /* 20h */
|
|
U16 IPVersion; /* 24h */
|
|
U16 UDPPortNumber; /* 26h */
|
|
U8 IPAddress[16]; /* 28h */
|
|
U16 Reserved1; /* 38h */
|
|
U16 TopologyDiscoveryFlags; /* 3Ah */
|
|
} CONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9,
|
|
FCPortPage9_t, MPI_POINTER pFCPortPage9_t;
|
|
|
|
#define MPI_FCPORTPAGE9_PAGEVERSION (0x00)
|
|
|
|
|
|
typedef struct _CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA
|
|
{
|
|
U8 Id; /* 10h */
|
|
U8 ExtId; /* 11h */
|
|
U8 Connector; /* 12h */
|
|
U8 Transceiver[8]; /* 13h */
|
|
U8 Encoding; /* 1Bh */
|
|
U8 BitRate_100mbs; /* 1Ch */
|
|
U8 Reserved1; /* 1Dh */
|
|
U8 Length9u_km; /* 1Eh */
|
|
U8 Length9u_100m; /* 1Fh */
|
|
U8 Length50u_10m; /* 20h */
|
|
U8 Length62p5u_10m; /* 21h */
|
|
U8 LengthCopper_m; /* 22h */
|
|
U8 Reseverved2; /* 22h */
|
|
U8 VendorName[16]; /* 24h */
|
|
U8 Reserved3; /* 34h */
|
|
U8 VendorOUI[3]; /* 35h */
|
|
U8 VendorPN[16]; /* 38h */
|
|
U8 VendorRev[4]; /* 48h */
|
|
U16 Reserved4; /* 4Ch */
|
|
U8 Reserved5; /* 4Eh */
|
|
U8 CC_BASE; /* 4Fh */
|
|
} CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,
|
|
MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,
|
|
FCPortPage10BaseSfpData_t, MPI_POINTER pFCPortPage10BaseSfpData_t;
|
|
|
|
#define MPI_FCPORT10_BASE_ID_UNKNOWN (0x00)
|
|
#define MPI_FCPORT10_BASE_ID_GBIC (0x01)
|
|
#define MPI_FCPORT10_BASE_ID_FIXED (0x02)
|
|
#define MPI_FCPORT10_BASE_ID_SFP (0x03)
|
|
#define MPI_FCPORT10_BASE_ID_SFP_MIN (0x04)
|
|
#define MPI_FCPORT10_BASE_ID_SFP_MAX (0x7F)
|
|
#define MPI_FCPORT10_BASE_ID_VEND_SPEC_MASK (0x80)
|
|
|
|
#define MPI_FCPORT10_BASE_EXTID_UNKNOWN (0x00)
|
|
#define MPI_FCPORT10_BASE_EXTID_MODDEF1 (0x01)
|
|
#define MPI_FCPORT10_BASE_EXTID_MODDEF2 (0x02)
|
|
#define MPI_FCPORT10_BASE_EXTID_MODDEF3 (0x03)
|
|
#define MPI_FCPORT10_BASE_EXTID_SEEPROM (0x04)
|
|
#define MPI_FCPORT10_BASE_EXTID_MODDEF5 (0x05)
|
|
#define MPI_FCPORT10_BASE_EXTID_MODDEF6 (0x06)
|
|
#define MPI_FCPORT10_BASE_EXTID_MODDEF7 (0x07)
|
|
#define MPI_FCPORT10_BASE_EXTID_VNDSPC_MASK (0x80)
|
|
|
|
#define MPI_FCPORT10_BASE_CONN_UNKNOWN (0x00)
|
|
#define MPI_FCPORT10_BASE_CONN_SC (0x01)
|
|
#define MPI_FCPORT10_BASE_CONN_COPPER1 (0x02)
|
|
#define MPI_FCPORT10_BASE_CONN_COPPER2 (0x03)
|
|
#define MPI_FCPORT10_BASE_CONN_BNC_TNC (0x04)
|
|
#define MPI_FCPORT10_BASE_CONN_COAXIAL (0x05)
|
|
#define MPI_FCPORT10_BASE_CONN_FIBERJACK (0x06)
|
|
#define MPI_FCPORT10_BASE_CONN_LC (0x07)
|
|
#define MPI_FCPORT10_BASE_CONN_MT_RJ (0x08)
|
|
#define MPI_FCPORT10_BASE_CONN_MU (0x09)
|
|
#define MPI_FCPORT10_BASE_CONN_SG (0x0A)
|
|
#define MPI_FCPORT10_BASE_CONN_OPT_PIGT (0x0B)
|
|
#define MPI_FCPORT10_BASE_CONN_RSV1_MIN (0x0C)
|
|
#define MPI_FCPORT10_BASE_CONN_RSV1_MAX (0x1F)
|
|
#define MPI_FCPORT10_BASE_CONN_HSSDC_II (0x20)
|
|
#define MPI_FCPORT10_BASE_CONN_CPR_PIGT (0x21)
|
|
#define MPI_FCPORT10_BASE_CONN_RSV2_MIN (0x22)
|
|
#define MPI_FCPORT10_BASE_CONN_RSV2_MAX (0x7F)
|
|
#define MPI_FCPORT10_BASE_CONN_VNDSPC_MASK (0x80)
|
|
|
|
#define MPI_FCPORT10_BASE_ENCODE_UNSPEC (0x00)
|
|
#define MPI_FCPORT10_BASE_ENCODE_8B10B (0x01)
|
|
#define MPI_FCPORT10_BASE_ENCODE_4B5B (0x02)
|
|
#define MPI_FCPORT10_BASE_ENCODE_NRZ (0x03)
|
|
#define MPI_FCPORT10_BASE_ENCODE_MANCHESTER (0x04)
|
|
|
|
|
|
typedef struct _CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA
|
|
{
|
|
U8 Options[2]; /* 50h */
|
|
U8 BitRateMax; /* 52h */
|
|
U8 BitRateMin; /* 53h */
|
|
U8 VendorSN[16]; /* 54h */
|
|
U8 DateCode[8]; /* 64h */
|
|
U8 Reserved5[3]; /* 6Ch */
|
|
U8 CC_EXT; /* 6Fh */
|
|
} CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,
|
|
MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,
|
|
FCPortPage10ExtendedSfpData_t, MPI_POINTER pFCPortPage10ExtendedSfpData_t;
|
|
|
|
#define MPI_FCPORT10_EXT_OPTION1_RATESEL (0x20)
|
|
#define MPI_FCPORT10_EXT_OPTION1_TX_DISABLE (0x10)
|
|
#define MPI_FCPORT10_EXT_OPTION1_TX_FAULT (0x08)
|
|
#define MPI_FCPORT10_EXT_OPTION1_LOS_INVERT (0x04)
|
|
#define MPI_FCPORT10_EXT_OPTION1_LOS (0x02)
|
|
|
|
|
|
typedef struct _CONFIG_PAGE_FC_PORT_10
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U8 Flags; /* 04h */
|
|
U8 Reserved1; /* 05h */
|
|
U16 Reserved2; /* 06h */
|
|
U32 HwConfig1; /* 08h */
|
|
U32 HwConfig2; /* 0Ch */
|
|
CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA Base; /* 10h */
|
|
CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA Extended; /* 50h */
|
|
U8 VendorSpecific[32]; /* 70h */
|
|
} CONFIG_PAGE_FC_PORT_10, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10,
|
|
FCPortPage10_t, MPI_POINTER pFCPortPage10_t;
|
|
|
|
#define MPI_FCPORTPAGE10_PAGEVERSION (0x00)
|
|
|
|
/* standard MODDEF pin definitions (from GBIC spec.) */
|
|
#define MPI_FCPORTPAGE10_FLAGS_MODDEF_MASK (0x00000007)
|
|
#define MPI_FCPORTPAGE10_FLAGS_MODDEF2 (0x00000001)
|
|
#define MPI_FCPORTPAGE10_FLAGS_MODDEF1 (0x00000002)
|
|
#define MPI_FCPORTPAGE10_FLAGS_MODDEF0 (0x00000004)
|
|
#define MPI_FCPORTPAGE10_FLAGS_MODDEF_NOGBIC (0x00000007)
|
|
#define MPI_FCPORTPAGE10_FLAGS_MODDEF_CPR_IEEE_CX (0x00000006)
|
|
#define MPI_FCPORTPAGE10_FLAGS_MODDEF_COPPER (0x00000005)
|
|
#define MPI_FCPORTPAGE10_FLAGS_MODDEF_OPTICAL_LW (0x00000004)
|
|
#define MPI_FCPORTPAGE10_FLAGS_MODDEF_SEEPROM (0x00000003)
|
|
#define MPI_FCPORTPAGE10_FLAGS_MODDEF_SW_OPTICAL (0x00000002)
|
|
#define MPI_FCPORTPAGE10_FLAGS_MODDEF_LX_IEEE_OPT_LW (0x00000001)
|
|
#define MPI_FCPORTPAGE10_FLAGS_MODDEF_SX_IEEE_OPT_SW (0x00000000)
|
|
|
|
#define MPI_FCPORTPAGE10_FLAGS_CC_BASE_OK (0x00000010)
|
|
#define MPI_FCPORTPAGE10_FLAGS_CC_EXT_OK (0x00000020)
|
|
|
|
|
|
/****************************************************************************
|
|
* FC Device Config Pages
|
|
****************************************************************************/
|
|
|
|
typedef struct _CONFIG_PAGE_FC_DEVICE_0
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U64 WWNN; /* 04h */
|
|
U64 WWPN; /* 0Ch */
|
|
U32 PortIdentifier; /* 14h */
|
|
U8 Protocol; /* 18h */
|
|
U8 Flags; /* 19h */
|
|
U16 BBCredit; /* 1Ah */
|
|
U16 MaxRxFrameSize; /* 1Ch */
|
|
U8 Reserved1; /* 1Eh */
|
|
U8 PortNumber; /* 1Fh */
|
|
U8 FcPhLowestVersion; /* 20h */
|
|
U8 FcPhHighestVersion; /* 21h */
|
|
U8 CurrentTargetID; /* 22h */
|
|
U8 CurrentBus; /* 23h */
|
|
} CONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0,
|
|
FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t;
|
|
|
|
#define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x02)
|
|
|
|
#define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01)
|
|
#define MPI_FC_DEVICE_PAGE0_FLAGS_PLOGI_INVALID (0x02)
|
|
#define MPI_FC_DEVICE_PAGE0_FLAGS_PRLI_INVALID (0x04)
|
|
|
|
#define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01)
|
|
#define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02)
|
|
#define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04)
|
|
|
|
#define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK)
|
|
#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK)
|
|
#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)
|
|
#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID)
|
|
#define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK)
|
|
#define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK)
|
|
#define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT)
|
|
#define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK)
|
|
|
|
|
|
/****************************************************************************
|
|
* RAID Volume Config Pages
|
|
****************************************************************************/
|
|
|
|
typedef struct _RAID_VOL0_PHYS_DISK
|
|
{
|
|
U16 Reserved; /* 00h */
|
|
U8 PhysDiskMap; /* 02h */
|
|
U8 PhysDiskNum; /* 03h */
|
|
} RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK,
|
|
RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t;
|
|
|
|
#define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
|
|
#define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
|
|
|
|
typedef struct _RAID_VOL0_STATUS
|
|
{
|
|
U8 Flags; /* 00h */
|
|
U8 State; /* 01h */
|
|
U16 Reserved; /* 02h */
|
|
} RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS,
|
|
RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t;
|
|
|
|
/* RAID Volume Page 0 VolumeStatus defines */
|
|
|
|
#define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01)
|
|
#define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02)
|
|
#define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04)
|
|
#define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x08)
|
|
|
|
#define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00)
|
|
#define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01)
|
|
#define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02)
|
|
|
|
typedef struct _RAID_VOL0_SETTINGS
|
|
{
|
|
U16 Settings; /* 00h */
|
|
U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */
|
|
U8 Reserved; /* 02h */
|
|
} RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS,
|
|
RaidVol0Settings, MPI_POINTER pRaidVol0Settings;
|
|
|
|
/* RAID Volume Page 0 VolumeSettings defines */
|
|
|
|
#define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001)
|
|
#define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002)
|
|
#define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004)
|
|
#define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008)
|
|
#define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010)
|
|
#define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000)
|
|
|
|
/* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
|
|
#define MPI_RAID_HOT_SPARE_POOL_0 (0x01)
|
|
#define MPI_RAID_HOT_SPARE_POOL_1 (0x02)
|
|
#define MPI_RAID_HOT_SPARE_POOL_2 (0x04)
|
|
#define MPI_RAID_HOT_SPARE_POOL_3 (0x08)
|
|
#define MPI_RAID_HOT_SPARE_POOL_4 (0x10)
|
|
#define MPI_RAID_HOT_SPARE_POOL_5 (0x20)
|
|
#define MPI_RAID_HOT_SPARE_POOL_6 (0x40)
|
|
#define MPI_RAID_HOT_SPARE_POOL_7 (0x80)
|
|
|
|
/*
|
|
* Host code (drivers, BIOS, utilities, etc.) should leave this define set to
|
|
* one and check Header.PageLength at runtime.
|
|
*/
|
|
#ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX
|
|
#define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
|
|
#endif
|
|
|
|
typedef struct _CONFIG_PAGE_RAID_VOL_0
|
|
{
|
|
CONFIG_PAGE_HEADER Header; /* 00h */
|
|
U8 VolumeID; /* 04h */
|
|
U8 VolumeBus; /* 05h */
|
|
U8 VolumeIOC; /* 06h */
|
|
U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */
|
|
RAID_VOL0_STATUS VolumeStatus; /* 08h */
|
|
RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */
|
|
U32 MaxLBA; /* 10h */
|
|
U32 Reserved1; /* 14h */
|
|
U32 StripeSize; /* 18h */
|
|
U32 Reserved2; /* 1Ch */
|
|
U32 Reserved3; /* 20h */
|
|
U8 NumPhysDisks; /* 24h */
|
|
U8 Reserved4; /* 25h */
|
|
U16 Reserved5; /* 26h */
|
|
RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */
|
|
} CONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0,
|
|
RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t;
|
|
|
|
#define MPI_RAIDVOLPAGE0_PAGEVERSION (0x01)
|
|
|
|
|
|
/****************************************************************************
|
|
* RAID Physical Disk Config Pages
|
|
****************************************************************************/
|
|
|
|
typedef struct _RAID_PHYS_DISK0_ERROR_DATA
|
|
{
|
|
U8 ErrorCdbByte; /* 00h */
|
|
U8 ErrorSenseKey; /* 01h */
|
|
U16 Reserved; /* 02h */
|
|
U16 ErrorCount; /* 04h */
|
|
U8 ErrorASC; /* 06h */
|
|
U8 ErrorASCQ; /* 07h */
|
|
U16 SmartCount; /* 08h */
|
|
U8 SmartASC; /* 0Ah */
|
|
U8 SmartASCQ; /* 0Bh */
|
|
} RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA,
|
|
RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t;
|
|
|
|
typedef struct _RAID_PHYS_DISK_INQUIRY_DATA
|
|
{
|
|
U8 VendorID[8]; /* 00h */
|
|
U8 ProductID[16]; /* 08h */
|
|
U8 ProductRevLevel[4]; /* 18h */
|
|
U8 Info[32]; /* 1Ch */
|
|
} RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA,
|
|
RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData;
|
|
|
|
typedef struct _RAID_PHYS_DISK0_SETTINGS
|
|
{
|
|
U8 SepID; /* 00h */
|
|
U8 SepBus; /* 01h */
|
|
U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */
|
|
U8 PhysDiskSettings; /* 03h */
|
|
} RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS,
|
|
RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t;
|
|
|
|
typedef struct _RAID_PHYS_DISK0_STATUS
|
|
{
|
|
U8 Flags; /* 00h */
|
|
U8 State; /* 01h */
|
|
U16 Reserved; /* 02h */
|
|
} RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS,
|
|
RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t;
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/* RAID Volume 2 IM Physical Disk DiskStatus flags */
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#define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01)
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#define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02)
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#define MPI_PHYSDISK0_STATUS_ONLINE (0x00)
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#define MPI_PHYSDISK0_STATUS_MISSING (0x01)
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#define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02)
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#define MPI_PHYSDISK0_STATUS_FAILED (0x03)
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#define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04)
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#define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05)
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#define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06)
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#define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF)
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typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0
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{
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CONFIG_PAGE_HEADER Header; /* 00h */
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U8 PhysDiskID; /* 04h */
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U8 PhysDiskBus; /* 05h */
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U8 PhysDiskIOC; /* 06h */
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U8 PhysDiskNum; /* 07h */
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RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */
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U32 Reserved1; /* 0Ch */
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U32 Reserved2; /* 10h */
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U32 Reserved3; /* 14h */
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U8 DiskIdentifier[16]; /* 18h */
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RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */
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RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */
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U32 MaxLBA; /* 68h */
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RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */
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} CONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0,
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RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t;
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#define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x00)
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/****************************************************************************
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* LAN Config Pages
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****************************************************************************/
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typedef struct _CONFIG_PAGE_LAN_0
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{
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ConfigPageHeader_t Header; /* 00h */
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U16 TxRxModes; /* 04h */
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U16 Reserved; /* 06h */
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U32 PacketPrePad; /* 08h */
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} CONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0,
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LANPage0_t, MPI_POINTER pLANPage0_t;
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#define MPI_LAN_PAGE0_PAGEVERSION (0x01)
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#define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000)
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#define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001)
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#define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001)
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typedef struct _CONFIG_PAGE_LAN_1
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{
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ConfigPageHeader_t Header; /* 00h */
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U16 Reserved; /* 04h */
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U8 CurrentDeviceState; /* 06h */
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U8 Reserved1; /* 07h */
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U32 MinPacketSize; /* 08h */
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U32 MaxPacketSize; /* 0Ch */
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U32 HardwareAddressLow; /* 10h */
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U32 HardwareAddressHigh; /* 14h */
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U32 MaxWireSpeedLow; /* 18h */
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U32 MaxWireSpeedHigh; /* 1Ch */
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U32 BucketsRemaining; /* 20h */
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U32 MaxReplySize; /* 24h */
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U32 NegWireSpeedLow; /* 28h */
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U32 NegWireSpeedHigh; /* 2Ch */
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} CONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1,
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LANPage1_t, MPI_POINTER pLANPage1_t;
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#define MPI_LAN_PAGE1_PAGEVERSION (0x03)
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#define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00)
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#define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01)
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#endif
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