475a76e3ce
copyright. When all member nations of the Buenos Aires Convention adopted the Berne Convention, the phrase "All rights reserved" became unnecessary to assert copyright. Remove it from files under my or Panasas's copyright. The files related to jedec_dimm(4) also bear avg@'s copyright; he has approved this change. Approved by: avg Sponsored by: Panasas
147 lines
5.5 KiB
C
147 lines
5.5 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Authors: Ravi Pokala (rpokala@freebsd.org)
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*
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* Copyright (c) 2018 Panasas
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV__JEDEC_DIMM__JEDEC_DIMM_H_
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#define _DEV__JEDEC_DIMM__JEDEC_DIMM_H_
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/* JEDEC DIMMs include one or more SMBus devices.
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*
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* At a minimum, they have an EEPROM containing either 256 bytes (DDR3) or 512
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* bytes (DDR4) of "Serial Presence Detect" (SPD) information. The SPD contains
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* data used by the memory controller to configure itself, and it also includes
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* asset information. The layout of SPD data is defined in:
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*
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* JEDEC Standard 21-C, Annex K (DDR3)
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* JEDEC Standard 21-C, Annex L (DDR4)
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*
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* DIMMs may also include a "Thermal Sensor on DIMM" (TSOD), which reports
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* temperature data. While not strictly required, the TSOD is so often included
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* that JEDEC defined standards for single chips which include both SPD and TSOD
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* functions. They respond on multiple SMBus addresses, depending on the
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* function.
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*
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* JEDEC Standard 21-C, TSE2002av (DDR3)
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* JEDEC Standard 21-C, TSE2004av (DDR4)
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*/
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/* TSE2004av defines several Device Type Identifiers (DTIs), which are the high
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* nybble of the SMBus address. Addresses with DTIs of PROTECT (or PAGE, which
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* has the same value) are essentially "broadcast" addresses; all SPD devices
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* respond to them, changing their mode based on the Logical Serial Address
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* (LSA) encoded in bits [3:1]. For normal SPD access, bits [3:1] encode the
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* DIMM slot number.
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*/
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#define JEDEC_SPD_PAGE_SIZE 256
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#define JEDEC_DTI_SPD 0xa0
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#define JEDEC_DTI_TSOD 0x30
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#define JEDEC_DTI_PROTECT 0x60
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#define JEDEC_LSA_PROTECT_SET0 0x02
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#define JEDEC_LSA_PROTECT_SET1 0x08
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#define JEDEC_LSA_PROTECT_SET2 0x0a
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#define JEDEC_LSA_PROTECT_SET3 0x00
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#define JEDEC_LSA_PROTECT_CLR 0x06
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#define JEDEC_LSA_PROTECT_GET0 0x03
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#define JEDEC_LSA_PROTECT_GET1 0x09
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#define JEDEC_LSA_PROTECT_GET2 0x0b
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#define JEDEC_LSA_PROTECT_GET3 0x01
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#define JEDEC_DTI_PAGE 0x60
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#define JEDEC_LSA_PAGE_SET0 0x0c
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#define JEDEC_LSA_PAGE_SET1 0x0e
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#define JEDEC_LSA_PAGE_GET 0x0d
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/* The offsets and lengths of various SPD bytes are defined in Annex K (DDR3)
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* and Annex L (DDR4). Conveniently, the DRAM type is at the same offset for
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* both versions.
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*
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* This list only includes information needed to get the asset information and
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* calculate the DIMM capacity.
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*/
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#define SPD_OFFSET_DRAM_TYPE 2
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#define SPD_OFFSET_DDR3_SDRAM_CAPACITY 4
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#define SPD_OFFSET_DDR3_DIMM_RANKS 7
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#define SPD_OFFSET_DDR3_SDRAM_WIDTH 7
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#define SPD_OFFSET_DDR3_BUS_WIDTH 8
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#define SPD_OFFSET_DDR3_TSOD_PRESENT 32
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#define SPD_OFFSET_DDR3_SERIAL 122
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#define SPD_LEN_DDR3_SERIAL 4
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#define SPD_OFFSET_DDR3_PARTNUM 128
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#define SPD_LEN_DDR3_PARTNUM 18
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#define SPD_OFFSET_DDR4_SDRAM_CAPACITY 4
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#define SPD_OFFSET_DDR4_SDRAM_PKG_TYPE 6
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#define SPD_OFFSET_DDR4_DIMM_RANKS 12
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#define SPD_OFFSET_DDR4_SDRAM_WIDTH 12
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#define SPD_OFFSET_DDR4_BUS_WIDTH 13
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#define SPD_OFFSET_DDR4_TSOD_PRESENT 14
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#define SPD_OFFSET_DDR4_SERIAL 325
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#define SPD_LEN_DDR4_SERIAL 4
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#define SPD_OFFSET_DDR4_PARTNUM 329
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#define SPD_LEN_DDR4_PARTNUM 20
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/* The "DRAM Type" field of the SPD enumerates various memory technologies which
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* have been used over the years. The list is append-only, so we need only refer
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* to the latest SPD specification. In this case, Annex L for DDR4.
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*/
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enum dram_type {
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DRAM_TYPE_RESERVED = 0x00,
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DRAM_TYPE_FAST_PAGE_MODE = 0x01,
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DRAM_TYPE_EDO = 0x02,
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DRAM_TYPE_PIPLEINED_NYBBLE = 0x03,
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DRAM_TYPE_SDRAM = 0x04,
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DRAM_TYPE_ROM = 0x05,
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DRAM_TYPE_DDR_SGRAM = 0x06,
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DRAM_TYPE_DDR_SDRAM = 0x07,
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DRAM_TYPE_DDR2_SDRAM = 0x08,
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DRAM_TYPE_DDR2_SDRAM_FBDIMM = 0x09,
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DRAM_TYPE_DDR2_SDRAM_FBDIMM_PROBE = 0x0a,
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DRAM_TYPE_DDR3_SDRAM = 0x0b,
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DRAM_TYPE_DDR4_SDRAM = 0x0c,
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DRAM_TYPE_RESERVED_0D = 0x0d,
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DRAM_TYPE_DDR4E_SDRAM = 0x0e,
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DRAM_TYPE_LPDDR3_SDRAM = 0x0f,
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DRAM_TYPE_LPDDR4_SDRAM = 0x10,
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};
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/* The TSOD is accessed using a simple word interface, which is identical
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* between TSE2002av (DDR3) and TSE2004av (DDR4).
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*/
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#define TSOD_REG_CAPABILITES 0
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#define TSOD_REG_CONFIG 1
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#define TSOD_REG_LIM_HIGH 2
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#define TSOD_REG_LIM_LOW 3
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#define TSOD_REG_LIM_CRIT 4
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#define TSOD_REG_TEMPERATURE 5
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#define TSOD_REG_MANUFACTURER 6
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#define TSOD_REG_DEV_REV 7
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#endif /* _DEV__JEDEC_DIMM__JEDEC_DIMM_H_ */
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/* vi: set ts=8 sw=4 sts=8 noet: */
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