04b6fa8330
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
157 lines
6.3 KiB
C
157 lines
6.3 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* cvmx-dbg-defs.h
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*
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* Configuration and status register (CSR) type definitions for
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* Octeon dbg.
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*
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* This file is auto generated. Do not edit.
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*
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* <hr>$Revision$<hr>
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*
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*/
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#ifndef __CVMX_DBG_TYPEDEFS_H__
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#define __CVMX_DBG_TYPEDEFS_H__
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_DBG_DATA CVMX_DBG_DATA_FUNC()
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static inline uint64_t CVMX_DBG_DATA_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
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cvmx_warn("CVMX_DBG_DATA not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x00011F00000001E8ull);
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}
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#else
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#define CVMX_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F00000001E8ull))
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#endif
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/**
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* cvmx_dbg_data
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*
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* DBG_DATA = Debug Data Register
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*
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* Value returned on the debug-data lines from the RSLs
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*/
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union cvmx_dbg_data
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{
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uint64_t u64;
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struct cvmx_dbg_data_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_23_63 : 41;
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uint64_t c_mul : 5; /**< C_MUL pins sampled at DCOK assertion */
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uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the
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debug select value. */
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uint64_t data : 17; /**< Value on the debug data lines. */
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#else
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uint64_t data : 17;
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uint64_t dsel_ext : 1;
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uint64_t c_mul : 5;
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uint64_t reserved_23_63 : 41;
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#endif
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} s;
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struct cvmx_dbg_data_cn30xx
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_31_63 : 33;
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uint64_t pll_mul : 3; /**< pll_mul pins sampled at DCOK assertion */
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uint64_t reserved_23_27 : 5;
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uint64_t c_mul : 5; /**< Core PLL multiplier sampled at DCOK assertion */
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uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the
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debug select value. */
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uint64_t data : 17; /**< Value on the debug data lines. */
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#else
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uint64_t data : 17;
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uint64_t dsel_ext : 1;
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uint64_t c_mul : 5;
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uint64_t reserved_23_27 : 5;
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uint64_t pll_mul : 3;
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uint64_t reserved_31_63 : 33;
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#endif
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} cn30xx;
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struct cvmx_dbg_data_cn30xx cn31xx;
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struct cvmx_dbg_data_cn38xx
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_29_63 : 35;
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uint64_t d_mul : 4; /**< D_MUL pins sampled on DCOK assertion */
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uint64_t dclk_mul2 : 1; /**< Should always be set for fast DDR-II operation */
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uint64_t cclk_div2 : 1; /**< Should always be clear for fast core clock */
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uint64_t c_mul : 5; /**< C_MUL pins sampled at DCOK assertion */
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uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the
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debug select value. */
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uint64_t data : 17; /**< Value on the debug data lines. */
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#else
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uint64_t data : 17;
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uint64_t dsel_ext : 1;
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uint64_t c_mul : 5;
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uint64_t cclk_div2 : 1;
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uint64_t dclk_mul2 : 1;
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uint64_t d_mul : 4;
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uint64_t reserved_29_63 : 35;
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#endif
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} cn38xx;
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struct cvmx_dbg_data_cn38xx cn38xxp2;
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struct cvmx_dbg_data_cn30xx cn50xx;
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struct cvmx_dbg_data_cn58xx
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_29_63 : 35;
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uint64_t rem : 6; /**< Remaining debug_select pins sampled at DCOK */
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uint64_t c_mul : 5; /**< C_MUL pins sampled at DCOK assertion */
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uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the
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debug select value. */
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uint64_t data : 17; /**< Value on the debug data lines. */
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#else
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uint64_t data : 17;
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uint64_t dsel_ext : 1;
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uint64_t c_mul : 5;
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uint64_t rem : 6;
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uint64_t reserved_29_63 : 35;
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#endif
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} cn58xx;
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struct cvmx_dbg_data_cn58xx cn58xxp1;
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};
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typedef union cvmx_dbg_data cvmx_dbg_data_t;
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#endif
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