8214ff0f9e
across the GICv2 and GICv3 drivers so we only need a single copy of them. Sponsored by: Turing Robotic Industries
103 lines
4.2 KiB
C
103 lines
4.2 KiB
C
/*-
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* Copyright (c) 2016 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Andrew Turner under
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* the sponsorship of the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _GIC_COMMON_H_
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#define _GIC_COMMON_H_
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#define GIC_IVAR_HW_REV 500
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#define GIC_IVAR_BUS 501
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/* GIC_IVAR_BUS values */
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#define GIC_BUS_UNKNOWN 0
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#define GIC_BUS_FDT 1
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#define GIC_BUS_ACPI 2
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#define GIC_BUS_MAX 2
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__BUS_ACCESSOR(gic, hw_rev, GIC, HW_REV, u_int);
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__BUS_ACCESSOR(gic, bus, GIC, BUS, u_int);
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/* Software Generated Interrupts */
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#define GIC_FIRST_SGI 0 /* Irqs 0-15 are SGIs/IPIs. */
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#define GIC_LAST_SGI 15
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/* Private Peripheral Interrupts */
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#define GIC_FIRST_PPI 16 /* Irqs 16-31 are private (per */
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#define GIC_LAST_PPI 31 /* core) peripheral interrupts. */
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/* Shared Peripheral Interrupts */
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#define GIC_FIRST_SPI 32 /* Irqs 32+ are shared peripherals. */
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/* Common register values */
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#define GICD_CTLR 0x0000 /* v1 ICDDCR */
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#define GICD_TYPER 0x0004 /* v1 ICDICTR */
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#define GICD_TYPER_I_NUM(n) ((((n) & 0x1F) + 1) * 32)
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#define GICD_IIDR 0x0008 /* v1 ICDIIDR */
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#define GICD_IIDR_PROD_SHIFT 24
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#define GICD_IIDR_PROD_MASK 0xff000000
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#define GICD_IIDR_PROD(x) \
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(((x) & GICD_IIDR_PROD_MASK) >> GICD_IIDR_PROD_SHIFT)
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#define GICD_IIDR_VAR_SHIFT 16
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#define GICD_IIDR_VAR_MASK 0x000f0000
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#define GICD_IIDR_VAR(x) \
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(((x) & GICD_IIDR_VAR_MASK) >> GICD_IIDR_VAR_SHIFT)
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#define GICD_IIDR_REV_SHIFT 12
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#define GICD_IIDR_REV_MASK 0x0000f000
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#define GICD_IIDR_REV(x) \
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(((x) & GICD_IIDR_REV_MASK) >> GICD_IIDR_REV_SHIFT)
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#define GICD_IIDR_IMPL_SHIFT 0
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#define GICD_IIDR_IMPL_MASK 0x00000fff
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#define GICD_IIDR_IMPL(x) \
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(((x) & GICD_IIDR_IMPL_MASK) >> GICD_IIDR_IMPL_SHIFT)
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#define GICD_IGROUPR(n) (0x0080 + (((n) >> 5) * 4)) /* v1 ICDISER */
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#define GICD_I_PER_IGROUPRn 32
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#define GICD_ISENABLER(n) (0x0100 + (((n) >> 5) * 4)) /* v1 ICDISER */
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#define GICD_I_MASK(n) (1ul << ((n) & 0x1f))
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#define GICD_I_PER_ISENABLERn 32
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#define GICD_ICENABLER(n) (0x0180 + (((n) >> 5) * 4)) /* v1 ICDICER */
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#define GICD_ISPENDR(n) (0x0200 + (((n) >> 5) * 4)) /* v1 ICDISPR */
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#define GICD_ICPENDR(n) (0x0280 + (((n) >> 5) * 4)) /* v1 ICDICPR */
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#define GICD_ICACTIVER(n) (0x0380 + (((n) >> 5) * 4)) /* v1 ICDABR */
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#define GICD_IPRIORITYR(n) (0x0400 + (((n) >> 2) * 4)) /* v1 ICDIPR */
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#define GICD_I_PER_IPRIORITYn 4
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#define GICD_ITARGETSR(n) (0x0800 + (((n) >> 2) * 4)) /* v1 ICDIPTR */
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#define GICD_ICFGR(n) (0x0C00 + (((n) >> 4) * 4)) /* v1 ICDICFR */
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#define GICD_I_PER_ICFGRn 16
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/* First bit is a polarity bit (0 - low, 1 - high) */
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#define GICD_ICFGR_POL_LOW (0 << 0)
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#define GICD_ICFGR_POL_HIGH (1 << 0)
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#define GICD_ICFGR_POL_MASK 0x1
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/* Second bit is a trigger bit (0 - level, 1 - edge) */
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#define GICD_ICFGR_TRIG_LVL (0 << 1)
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#define GICD_ICFGR_TRIG_EDGE (1 << 1)
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#define GICD_ICFGR_TRIG_MASK 0x2
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#define GICD_SGIR 0x0F00 /* v1 ICDSGIR */
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#define GICD_SGI_TARGET_SHIFT 16
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#endif /* _GIC_COMMON_H_ */
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