7f725bcd5c
The NAND Flash environment consists of several distinct components: - NAND framework (drivers harness for NAND controllers and NAND chips) - NAND simulator (NANDsim) - NAND file system (NAND FS) - Companion tools and utilities - Documentation (manual pages) This work is still experimental. Please use with caution. Obtained from: Semihalf Supported by: FreeBSD Foundation, Juniper Networks
175 lines
5.1 KiB
Plaintext
175 lines
5.1 KiB
Plaintext
#-
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# Copyright (C) 2009-2012 Semihalf
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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# 1. Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# 2. Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution.
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#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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# SUCH DAMAGE.
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#
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# $FreeBSD$
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#
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# Sample NANDsim configuration file.
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#
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#############################################################################
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#
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# [sim] General (common) simulator configuration section.
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#
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[sim]
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# log_level=0..255
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log_level=11
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# log_output=[none, console, ram, file]
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#
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# When log_output=file is specified, each [ctrl] section must have a
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# corresponding 'log_filename' field provided, which specifies log file name
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# to be used.
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log_output=none
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#############################################################################
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#
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# [ctrl] Controller configuration section.
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#
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# There can be a number of controllers defined for simulation, each has a
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# dedicated [ctrl] section. With a given controller there are associated
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# subordinate NAND chips, which are tied to chip select lines.
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#
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[ctrl]
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# The number of this controller.
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# ctrl_num=0..3
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ctrl_num=0
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# The number of chip selects available at this controller.
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# num_cs=1..4
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num_cs=1
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# ECC enable flag.
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# ecc=[on|off]
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ecc=on
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# ECC layout. This is the list of byte offsets within OOB area, which comprise
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# the ECC contents set.
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#
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# ecc_layout=[byte1, byte2-byte3, ..byten]
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ecc_layout=[0-53]
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# Absolute path to the log file for this controller.
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#log_filename=/var/log/nandsim-ctl0.log
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#############################################################################
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#
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# [chip] Chip configuration section.
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#
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# There can be a number of individual NAND chip devices defined for
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# simulation, and each has a dedicated [chip] section.
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#
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# A particular chip needs to be associated with its parent NAND controller by
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# specifying the following fields: controller number (chip_ctrl) and the chip
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# select line it is connected to (chip_cs). The chip can be connected to only
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# a single (and unique) controller:cs pair.
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#
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[chip]
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# The number of parent controller. This has to fit one of the controller
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# instance number (ctrl_num from [ctrl] section).
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# chip_ctrl=0..3
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chip_ctrl=0
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# Chip select line.
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# chip_cs=0..3
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chip_cs=0
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# ONFI device identifier.
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# device_id=0x00..0xff
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device_id=0xd3
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# ONFI manufacturer identifier.
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# manufacturer_id=0x00..0xff
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manufacturer_id=0xec
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# Textual description of the chip.
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# model="model_name"
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model="k9xxg08uxM:1GiB 3,3V 8-bit"
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# Textual name of the chip manufacturer.
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# manufacturer="manufacturer name"
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manufacturer="SAMSUNG"
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# page_size=[must be power of 2 and >= 512] (in bytes)
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page_size=2048
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# oob_size=[>0]
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oob_size=64
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# pages_per_block=n*32
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pages_per_block=64
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# blocks_per_lun=[>0]
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blocks_per_lun=4096
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# luns=1..N
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luns=1
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# column_addr_cycle=[1,2]
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column_addr_cycle=2
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# row_addr_cycle=[1,2,3]
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row_addr_cycle=3
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# program_time= (in us)
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program_time=0
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# erase_time= (in us)
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erase_time=0
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# read_time= (in us)
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read_time=0
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# ccs_time= (in us)
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#ccs_time=200
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# Simulate write-protect on the chip.
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# write_protect=[yes|no]
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#write_protect=no
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# Blocks wear-out threshold. Each block has a counter of program-erase cycles;
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# when this counter reaches 'wear_out' value a given block is treated as a bad
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# block (access will report error).
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#
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# Setting wear_out to 0 means that blocks will never wear out.
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#
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# wear_out=0..100000
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wear_out=50000
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# Errors per million read/write bytes. This simulates an accidental read/write
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# block error, which can happen in real devices with certain probability. Note
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# this isn't a bad block condition i.e. the block at which the read/write
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# operation is simulated to fail here remains usable, only the operation has
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# not succeeded (this is where ECC comes into play and is supposed to correct
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# such problems).
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#
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# error_ratio=0..1000000
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#error_ratio=50
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# Chip data bus width. All chips connected to the same controller must have
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# the same bus width.
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#
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# width=[8|16]
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width=8
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# Bad block map. NANDsim emulates bad block behavior upon accessing a block
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# with number from the specified list.
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#
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# bad_block_map=[bad_block1, bad_block2-bad_block3, ..bad_blockn]
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bad_block_map=[100-200]
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