28029b68c0
This is the final step required allowing to compile and to run RISC-V kernel and userland from HEAD. RISC-V is a completely open ISA that is freely available to academia and industry. Thanks to all the people involved! Special thanks to Andrew Turner, David Chisnall, Ed Maste, Konstantin Belousov, John Baldwin and Arun Thomas for their help. Thanks to Robert Watson for organizing this project. This project sponsored by UK Higher Education Innovation Fund (HEIF5) and DARPA CTSRD project at the University of Cambridge Computer Laboratory. FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv Reviewed by: andrew, emaste, kib Relnotes: Yes Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D4982
94 lines
3.2 KiB
C
94 lines
3.2 KiB
C
/*-
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* Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Portions of this software were developed by SRI International and the
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* University of Cambridge Computer Laboratory under DARPA/AFRL contract
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* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Portions of this software were developed by the University of Cambridge
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* Computer Laboratory as part of the CTSRD Project, with support from the
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* UK Higher Education Innovation Fund (HEIF).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define HTIF_DEV_ID_SHIFT (56)
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#define HTIF_DEV_ID_MASK (0xfful << HTIF_DEV_ID_SHIFT)
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#define HTIF_CMD_SHIFT (48)
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#define HTIF_CMD_MASK (0xfful << HTIF_CMD_SHIFT)
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#define HTIF_DATA_SHIFT (0)
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#define HTIF_DATA_MASK (0xffffffff << HTIF_DATA_SHIFT)
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#define HTIF_CMD_READ (0x00ul)
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#define HTIF_CMD_WRITE (0x01ul)
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#define HTIF_CMD_READ_CONTROL_REG (0x02ul)
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#define HTIF_CMD_WRITE_CONTROL_REG (0x03ul)
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#define HTIF_CMD_IDENTIFY (0xfful)
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#define IDENTIFY_PADDR_SHIFT 8
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#define IDENTIFY_IDENT 0xff
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#define HTIF_NDEV (256)
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#define HTIF_ID_LEN (64)
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#define HTIF_ALIGN (64)
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#define HTIF_DEV_CMD(entry) ((entry & HTIF_CMD_MASK) >> HTIF_CMD_SHIFT)
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#define HTIF_DEV_ID(entry) ((entry & HTIF_DEV_ID_MASK) >> HTIF_DEV_ID_SHIFT)
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#define HTIF_DEV_DATA(entry) ((entry & HTIF_DATA_MASK) >> HTIF_DATA_SHIFT)
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/* bus softc */
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struct htif_softc {
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struct resource *res[1];
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void *ihl[1];
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device_t dev;
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uint64_t identify_id;
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uint64_t identify_done;
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};
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/* device private data */
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struct htif_dev_ivars {
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char *id;
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int index;
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device_t dev;
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struct htif_softc *sc;
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};
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uint64_t htif_command(uint64_t);
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int htif_setup_intr(int id, void *func, void *arg);
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int htif_read_ivar(device_t dev, device_t child, int which, uintptr_t *result);
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enum htif_device_ivars {
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HTIF_IVAR_INDEX,
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HTIF_IVAR_ID,
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};
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/*
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* Simplified accessors for HTIF devices
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*/
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#define HTIF_ACCESSOR(var, ivar, type) \
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__BUS_ACCESSOR(htif, var, HTIF, ivar, type)
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HTIF_ACCESSOR(index, INDEX, int);
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HTIF_ACCESSOR(id, ID, char *);
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