04b6fa8330
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
435 lines
16 KiB
C
435 lines
16 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* cvmx-zip-defs.h
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*
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* Configuration and status register (CSR) type definitions for
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* Octeon zip.
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*
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* This file is auto generated. Do not edit.
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*
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* <hr>$Revision$<hr>
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*
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*/
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#ifndef __CVMX_ZIP_TYPEDEFS_H__
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#define __CVMX_ZIP_TYPEDEFS_H__
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_ZIP_CMD_BIST_RESULT CVMX_ZIP_CMD_BIST_RESULT_FUNC()
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static inline uint64_t CVMX_ZIP_CMD_BIST_RESULT_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
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cvmx_warn("CVMX_ZIP_CMD_BIST_RESULT not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180038000080ull);
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}
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#else
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#define CVMX_ZIP_CMD_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180038000080ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_ZIP_CMD_BUF CVMX_ZIP_CMD_BUF_FUNC()
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static inline uint64_t CVMX_ZIP_CMD_BUF_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
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cvmx_warn("CVMX_ZIP_CMD_BUF not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180038000008ull);
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}
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#else
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#define CVMX_ZIP_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180038000008ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_ZIP_CMD_CTL CVMX_ZIP_CMD_CTL_FUNC()
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static inline uint64_t CVMX_ZIP_CMD_CTL_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
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cvmx_warn("CVMX_ZIP_CMD_CTL not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180038000000ull);
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}
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#else
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#define CVMX_ZIP_CMD_CTL (CVMX_ADD_IO_SEG(0x0001180038000000ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_ZIP_CONSTANTS CVMX_ZIP_CONSTANTS_FUNC()
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static inline uint64_t CVMX_ZIP_CONSTANTS_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
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cvmx_warn("CVMX_ZIP_CONSTANTS not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x00011800380000A0ull);
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}
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#else
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#define CVMX_ZIP_CONSTANTS (CVMX_ADD_IO_SEG(0x00011800380000A0ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_ZIP_DEBUG0 CVMX_ZIP_DEBUG0_FUNC()
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static inline uint64_t CVMX_ZIP_DEBUG0_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
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cvmx_warn("CVMX_ZIP_DEBUG0 not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180038000098ull);
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}
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#else
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#define CVMX_ZIP_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180038000098ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_ZIP_ERROR CVMX_ZIP_ERROR_FUNC()
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static inline uint64_t CVMX_ZIP_ERROR_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
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cvmx_warn("CVMX_ZIP_ERROR not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180038000088ull);
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}
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#else
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#define CVMX_ZIP_ERROR (CVMX_ADD_IO_SEG(0x0001180038000088ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_ZIP_INT_MASK CVMX_ZIP_INT_MASK_FUNC()
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static inline uint64_t CVMX_ZIP_INT_MASK_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
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cvmx_warn("CVMX_ZIP_INT_MASK not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180038000090ull);
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}
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#else
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#define CVMX_ZIP_INT_MASK (CVMX_ADD_IO_SEG(0x0001180038000090ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_ZIP_THROTTLE CVMX_ZIP_THROTTLE_FUNC()
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static inline uint64_t CVMX_ZIP_THROTTLE_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
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cvmx_warn("CVMX_ZIP_THROTTLE not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180038000010ull);
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}
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#else
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#define CVMX_ZIP_THROTTLE (CVMX_ADD_IO_SEG(0x0001180038000010ull))
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#endif
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/**
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* cvmx_zip_cmd_bist_result
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*
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* Notes:
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* Access to the internal BiST results
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* Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
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*/
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union cvmx_zip_cmd_bist_result
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{
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uint64_t u64;
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struct cvmx_zip_cmd_bist_result_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_43_63 : 21;
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uint64_t zip_core : 39; /**< BiST result of the ZIP_CORE memories */
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uint64_t zip_ctl : 4; /**< BiST result of the ZIP_CTL memories */
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#else
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uint64_t zip_ctl : 4;
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uint64_t zip_core : 39;
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uint64_t reserved_43_63 : 21;
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#endif
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} s;
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struct cvmx_zip_cmd_bist_result_cn31xx
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_31_63 : 33;
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uint64_t zip_core : 27; /**< BiST result of the ZIP_CORE memories */
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uint64_t zip_ctl : 4; /**< BiST result of the ZIP_CTL memories */
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#else
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uint64_t zip_ctl : 4;
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uint64_t zip_core : 27;
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uint64_t reserved_31_63 : 33;
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#endif
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} cn31xx;
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struct cvmx_zip_cmd_bist_result_cn31xx cn38xx;
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struct cvmx_zip_cmd_bist_result_cn31xx cn38xxp2;
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struct cvmx_zip_cmd_bist_result_cn31xx cn56xx;
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struct cvmx_zip_cmd_bist_result_cn31xx cn56xxp1;
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struct cvmx_zip_cmd_bist_result_cn31xx cn58xx;
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struct cvmx_zip_cmd_bist_result_cn31xx cn58xxp1;
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struct cvmx_zip_cmd_bist_result_s cn63xx;
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struct cvmx_zip_cmd_bist_result_s cn63xxp1;
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};
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typedef union cvmx_zip_cmd_bist_result cvmx_zip_cmd_bist_result_t;
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/**
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* cvmx_zip_cmd_buf
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*
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* Notes:
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* Sets the command buffer parameters
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* The size of the command buffer segments is measured in uint64s. The pool specifies (1 of 8 free
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* lists to be used when freeing command buffer segments. The PTR field is overwritten with the next
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* pointer each time that the command buffer segment is exhausted.
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* When quiescent (i.e. outstanding doorbell count is 0), it is safe to rewrite
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* this register to effectively reset the command buffer state machine. New commands will then be
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* read from the newly specified command buffer pointer.
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*/
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union cvmx_zip_cmd_buf
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{
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uint64_t u64;
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struct cvmx_zip_cmd_buf_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_58_63 : 6;
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uint64_t dwb : 9; /**< Number of DontWriteBacks */
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uint64_t pool : 3; /**< Free list used to free command buffer segments */
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uint64_t size : 13; /**< Number of uint64s per command buffer segment */
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uint64_t ptr : 33; /**< Initial command buffer pointer[39:7] (128B-aligned) */
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#else
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uint64_t ptr : 33;
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uint64_t size : 13;
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uint64_t pool : 3;
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uint64_t dwb : 9;
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uint64_t reserved_58_63 : 6;
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#endif
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} s;
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struct cvmx_zip_cmd_buf_s cn31xx;
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struct cvmx_zip_cmd_buf_s cn38xx;
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struct cvmx_zip_cmd_buf_s cn38xxp2;
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struct cvmx_zip_cmd_buf_s cn56xx;
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struct cvmx_zip_cmd_buf_s cn56xxp1;
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struct cvmx_zip_cmd_buf_s cn58xx;
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struct cvmx_zip_cmd_buf_s cn58xxp1;
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struct cvmx_zip_cmd_buf_s cn63xx;
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struct cvmx_zip_cmd_buf_s cn63xxp1;
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};
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typedef union cvmx_zip_cmd_buf cvmx_zip_cmd_buf_t;
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/**
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* cvmx_zip_cmd_ctl
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*/
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union cvmx_zip_cmd_ctl
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{
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uint64_t u64;
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struct cvmx_zip_cmd_ctl_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_2_63 : 62;
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uint64_t forceclk : 1; /**< Force zip_ctl__clock_on_b == 1 when set */
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uint64_t reset : 1; /**< Reset oneshot pulse for zip core */
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#else
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uint64_t reset : 1;
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uint64_t forceclk : 1;
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uint64_t reserved_2_63 : 62;
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#endif
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} s;
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struct cvmx_zip_cmd_ctl_s cn31xx;
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struct cvmx_zip_cmd_ctl_s cn38xx;
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struct cvmx_zip_cmd_ctl_s cn38xxp2;
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struct cvmx_zip_cmd_ctl_s cn56xx;
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struct cvmx_zip_cmd_ctl_s cn56xxp1;
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struct cvmx_zip_cmd_ctl_s cn58xx;
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struct cvmx_zip_cmd_ctl_s cn58xxp1;
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struct cvmx_zip_cmd_ctl_s cn63xx;
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struct cvmx_zip_cmd_ctl_s cn63xxp1;
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};
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typedef union cvmx_zip_cmd_ctl cvmx_zip_cmd_ctl_t;
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/**
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* cvmx_zip_constants
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*
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* Notes:
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* Note that this CSR is present only in chip revisions beginning with pass2.
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*
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*/
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union cvmx_zip_constants
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{
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uint64_t u64;
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struct cvmx_zip_constants_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_48_63 : 16;
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uint64_t depth : 16; /**< Maximum search depth for compression */
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uint64_t onfsize : 12; /**< Output near full threshhold in bytes */
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uint64_t ctxsize : 12; /**< Context size in bytes */
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uint64_t reserved_1_7 : 7;
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uint64_t disabled : 1; /**< 1=zip unit isdisabled, 0=zip unit not disabled */
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#else
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uint64_t disabled : 1;
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uint64_t reserved_1_7 : 7;
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uint64_t ctxsize : 12;
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uint64_t onfsize : 12;
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uint64_t depth : 16;
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uint64_t reserved_48_63 : 16;
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#endif
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} s;
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struct cvmx_zip_constants_s cn31xx;
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struct cvmx_zip_constants_s cn38xx;
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struct cvmx_zip_constants_s cn38xxp2;
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struct cvmx_zip_constants_s cn56xx;
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struct cvmx_zip_constants_s cn56xxp1;
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struct cvmx_zip_constants_s cn58xx;
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struct cvmx_zip_constants_s cn58xxp1;
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struct cvmx_zip_constants_s cn63xx;
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struct cvmx_zip_constants_s cn63xxp1;
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};
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typedef union cvmx_zip_constants cvmx_zip_constants_t;
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/**
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* cvmx_zip_debug0
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*
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* Notes:
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* Note that this CSR is present only in chip revisions beginning with pass2.
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*
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*/
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union cvmx_zip_debug0
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{
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uint64_t u64;
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struct cvmx_zip_debug0_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_17_63 : 47;
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uint64_t asserts : 17; /**< FIFO assertion checks */
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#else
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uint64_t asserts : 17;
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uint64_t reserved_17_63 : 47;
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#endif
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} s;
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struct cvmx_zip_debug0_cn31xx
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_14_63 : 50;
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uint64_t asserts : 14; /**< FIFO assertion checks */
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#else
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uint64_t asserts : 14;
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uint64_t reserved_14_63 : 50;
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#endif
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} cn31xx;
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struct cvmx_zip_debug0_cn31xx cn38xx;
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struct cvmx_zip_debug0_cn31xx cn38xxp2;
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struct cvmx_zip_debug0_cn31xx cn56xx;
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struct cvmx_zip_debug0_cn31xx cn56xxp1;
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struct cvmx_zip_debug0_cn31xx cn58xx;
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struct cvmx_zip_debug0_cn31xx cn58xxp1;
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struct cvmx_zip_debug0_s cn63xx;
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struct cvmx_zip_debug0_s cn63xxp1;
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};
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typedef union cvmx_zip_debug0 cvmx_zip_debug0_t;
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/**
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* cvmx_zip_error
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*
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* Notes:
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* Note that this CSR is present only in chip revisions beginning with pass2.
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*
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*/
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union cvmx_zip_error
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{
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uint64_t u64;
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struct cvmx_zip_error_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_1_63 : 63;
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uint64_t doorbell : 1; /**< A doorbell count has overflowed */
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#else
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uint64_t doorbell : 1;
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uint64_t reserved_1_63 : 63;
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#endif
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} s;
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struct cvmx_zip_error_s cn31xx;
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struct cvmx_zip_error_s cn38xx;
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struct cvmx_zip_error_s cn38xxp2;
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struct cvmx_zip_error_s cn56xx;
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struct cvmx_zip_error_s cn56xxp1;
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struct cvmx_zip_error_s cn58xx;
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struct cvmx_zip_error_s cn58xxp1;
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struct cvmx_zip_error_s cn63xx;
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struct cvmx_zip_error_s cn63xxp1;
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};
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typedef union cvmx_zip_error cvmx_zip_error_t;
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/**
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* cvmx_zip_int_mask
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*
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* Notes:
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* Note that this CSR is present only in chip revisions beginning with pass2.
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* When a mask bit is set, the corresponding interrupt is enabled.
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*/
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union cvmx_zip_int_mask
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{
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uint64_t u64;
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struct cvmx_zip_int_mask_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_1_63 : 63;
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uint64_t doorbell : 1; /**< Bit mask corresponding to ZIP_ERROR[0] above */
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#else
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uint64_t doorbell : 1;
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uint64_t reserved_1_63 : 63;
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#endif
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} s;
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struct cvmx_zip_int_mask_s cn31xx;
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struct cvmx_zip_int_mask_s cn38xx;
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|
struct cvmx_zip_int_mask_s cn38xxp2;
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|
struct cvmx_zip_int_mask_s cn56xx;
|
|
struct cvmx_zip_int_mask_s cn56xxp1;
|
|
struct cvmx_zip_int_mask_s cn58xx;
|
|
struct cvmx_zip_int_mask_s cn58xxp1;
|
|
struct cvmx_zip_int_mask_s cn63xx;
|
|
struct cvmx_zip_int_mask_s cn63xxp1;
|
|
};
|
|
typedef union cvmx_zip_int_mask cvmx_zip_int_mask_t;
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|
|
|
/**
|
|
* cvmx_zip_throttle
|
|
*
|
|
* Notes:
|
|
* The maximum number of inflight data fetch transactions. Values > 8 are illegal.
|
|
* Writing 0 to this register causes the ZIP module to temporarily suspend NCB
|
|
* accesses; it is not recommended for normal operation, but may be useful for
|
|
* diagnostics.
|
|
*/
|
|
union cvmx_zip_throttle
|
|
{
|
|
uint64_t u64;
|
|
struct cvmx_zip_throttle_s
|
|
{
|
|
#if __BYTE_ORDER == __BIG_ENDIAN
|
|
uint64_t reserved_4_63 : 60;
|
|
uint64_t max_infl : 4; /**< Maximum number of inflight data fetch transactions on NCB */
|
|
#else
|
|
uint64_t max_infl : 4;
|
|
uint64_t reserved_4_63 : 60;
|
|
#endif
|
|
} s;
|
|
struct cvmx_zip_throttle_s cn63xx;
|
|
struct cvmx_zip_throttle_s cn63xxp1;
|
|
};
|
|
typedef union cvmx_zip_throttle cvmx_zip_throttle_t;
|
|
|
|
#endif
|