04b6fa8330
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
143 lines
5.2 KiB
C
143 lines
5.2 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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#ifndef __OCTEON_PCI_CONSOLE_H__
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#define __OCTEON_PCI_CONSOLE_H__
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#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
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#include "cvmx-platform.h"
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#endif
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/* Current versions */
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#define OCTEON_PCI_CONSOLE_MAJOR_VERSION 1
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#define OCTEON_PCI_CONSOLE_MINOR_VERSION 0
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#define OCTEON_PCI_CONSOLE_BLOCK_NAME "__pci_console"
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/* Structure that defines a single console.
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* Note: when read_index == write_index, the buffer is empty. The actual usable size
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* of each console is console_buf_size -1;
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*/
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typedef struct {
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uint64_t input_base_addr;
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uint32_t input_read_index;
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uint32_t input_write_index;
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uint64_t output_base_addr;
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uint32_t output_read_index;
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uint32_t output_write_index;
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uint32_t lock;
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uint32_t buf_size;
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} octeon_pci_console_t;
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/* This is the main container structure that contains all the information
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about all PCI consoles. The address of this structure is passed to various
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routines that operation on PCI consoles.
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*/
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typedef struct {
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uint32_t major_version;
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uint32_t minor_version;
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uint32_t lock;
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uint32_t flags;
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uint32_t num_consoles;
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uint32_t pad;
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/* must be 64 bit aligned here... */
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uint64_t console_addr_array[0]; /* Array of addresses of octeon_pci_console_t structures */
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/* Implicit storage for console_addr_array */
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} octeon_pci_console_desc_t;
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/* Flag definitions for octeon_pci_console_desc_t */
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enum {
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OCT_PCI_CON_DESC_FLAG_PERCPU = 1 << 0, /* If set, output from core N will be sent to console N */
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};
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#if defined(OCTEON_TARGET) && !defined(__linux__)
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/**
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* This is an internal-only function that is called from within the simple executive
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* C library, and is not intended for any other use.
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*
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* @param fd
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* @param buf
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* @param nbytes
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*
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* @return
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*/
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int __cvmx_pci_console_write (int fd, char *buf, int nbytes);
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#endif
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#ifdef CVMX_BUILD_FOR_UBOOT
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uint64_t octeon_pci_console_init(int num_consoles, int buffer_size);
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#endif
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/* Flag definitions for read/write functions */
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enum {
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OCT_PCI_CON_FLAG_NONBLOCK = 1 << 0, /* If set, read/write functions won't block waiting for space or data.
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* For reads, 0 bytes may be read, and for writes not all of the
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* supplied data may be written.*/
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};
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#if !defined(__linux__) || defined(__KERNEL__)
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int octeon_pci_console_write(uint64_t console_desc_addr, unsigned int console_num, const char * buffer, int bytes_to_write, uint32_t flags);
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int octeon_pci_console_write_avail(uint64_t console_desc_addr, unsigned int console_num);
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int octeon_pci_console_read(uint64_t console_desc_addr, unsigned int console_num, char * buffer, int buffer_size, uint32_t flags);
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int octeon_pci_console_read_avail(uint64_t console_desc_addr, unsigned int console_num);
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#endif
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#if !defined(OCTEON_TARGET) && defined(__linux__) && !defined(__KERNEL__)
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int octeon_pci_console_host_write(uint64_t console_desc_addr, unsigned int console_num, const char * buffer, int write_reqest_size, uint32_t flags);
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int octeon_pci_console_host_write_avail(uint64_t console_desc_addr, unsigned int console_num);
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int octeon_pci_console_host_read(uint64_t console_desc_addr, unsigned int console_num, char * buffer, int buf_size, uint32_t flags);
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int octeon_pci_console_host_read_avail(uint64_t console_desc_addr, unsigned int console_num);
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#endif
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#endif
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