926f4e43c6
enable IDE I/O" bit which prevents data access traps with revision 0xc8 in Fire-based machines when pci(4) enables PCIM_CMD_PORTEN. - Like for sun4v also don't add the PCI side of host-PCIe bridges to the bus on sun4u as they don't have configuration space implement there either.
341 lines
11 KiB
C
341 lines
11 KiB
C
/*-
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* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
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* Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
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* Copyright (c) 2000, BSDi
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* Copyright (c) 2003, Thomas Moestl <tmm@FreeBSD.org>
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* Copyright (c) 2005 - 2009 Marius Strobl <marius@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ofw_pci.h"
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/libkern.h>
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#include <sys/module.h>
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#include <sys/pciio.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_pci.h>
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#include <dev/ofw/openfirm.h>
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#include <machine/bus.h>
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#ifndef SUN4V
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#include <machine/bus_common.h>
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#include <machine/iommureg.h>
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#endif
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#include <machine/resource.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pci_private.h>
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#include <sparc64/pci/ofw_pci.h>
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#include "pcib_if.h"
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#include "pci_if.h"
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/* Helper functions */
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static void ofw_pcibus_setup_device(device_t bridge, uint32_t clock,
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u_int busno, u_int slot, u_int func);
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/* Methods */
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static bus_child_pnpinfo_str_t ofw_pcibus_pnpinfo_str;
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static device_attach_t ofw_pcibus_attach;
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static device_probe_t ofw_pcibus_probe;
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static ofw_bus_get_devinfo_t ofw_pcibus_get_devinfo;
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static pci_assign_interrupt_t ofw_pcibus_assign_interrupt;
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static device_method_t ofw_pcibus_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, ofw_pcibus_probe),
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DEVMETHOD(device_attach, ofw_pcibus_attach),
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/* Bus interface */
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DEVMETHOD(bus_child_pnpinfo_str, ofw_pcibus_pnpinfo_str),
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/* PCI interface */
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DEVMETHOD(pci_assign_interrupt, ofw_pcibus_assign_interrupt),
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/* ofw_bus interface */
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DEVMETHOD(ofw_bus_get_devinfo, ofw_pcibus_get_devinfo),
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DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
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DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
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DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
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DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
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DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
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KOBJMETHOD_END
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};
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struct ofw_pcibus_devinfo {
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struct pci_devinfo opd_dinfo;
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struct ofw_bus_devinfo opd_obdinfo;
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};
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static devclass_t pci_devclass;
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DEFINE_CLASS_1(pci, ofw_pcibus_driver, ofw_pcibus_methods, 1 /* no softc */,
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pci_driver);
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EARLY_DRIVER_MODULE(ofw_pcibus, pcib, ofw_pcibus_driver, pci_devclass, 0, 0,
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BUS_PASS_BUS);
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MODULE_VERSION(ofw_pcibus, 1);
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MODULE_DEPEND(ofw_pcibus, pci, 1, 1, 1);
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static int
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ofw_pcibus_probe(device_t dev)
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{
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if (ofw_bus_get_node(dev) == 0)
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return (ENXIO);
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device_set_desc(dev, "OFW PCI bus");
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return (0);
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}
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/*
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* Perform miscellaneous setups the firmware usually does not do for us.
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*/
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static void
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ofw_pcibus_setup_device(device_t bridge, uint32_t clock, u_int busno,
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u_int slot, u_int func)
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{
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#define CS_READ(n, w) \
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PCIB_READ_CONFIG(bridge, busno, slot, func, (n), (w))
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#define CS_WRITE(n, v, w) \
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PCIB_WRITE_CONFIG(bridge, busno, slot, func, (n), (v), (w))
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#ifndef SUN4V
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uint32_t reg;
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/*
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* Initialize the latency timer register for busmaster devices to
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* work properly. This is another task which the firmware doesn't
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* always perform. The Min_Gnt register can be used to compute its
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* recommended value: it contains the desired latency in units of
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* 1/4 us assuming a clock rate of 33MHz. To calculate the correct
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* latency timer value, the clock frequency of the bus (defaulting
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* to 33MHz) should be used and no wait states assumed.
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* For bridges, we additionally set up the bridge control and the
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* secondary latency registers.
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*/
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if ((CS_READ(PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) ==
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PCIM_HDRTYPE_BRIDGE) {
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reg = CS_READ(PCIR_BRIDGECTL_1, 1);
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reg |= PCIB_BCR_MASTER_ABORT_MODE | PCIB_BCR_SERR_ENABLE |
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PCIB_BCR_PERR_ENABLE;
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#ifdef OFW_PCI_DEBUG
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device_printf(bridge,
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"bridge %d/%d/%d: control 0x%x -> 0x%x\n",
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busno, slot, func, CS_READ(PCIR_BRIDGECTL_1, 1), reg);
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#endif /* OFW_PCI_DEBUG */
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CS_WRITE(PCIR_BRIDGECTL_1, reg, 1);
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reg = OFW_PCI_LATENCY;
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#ifdef OFW_PCI_DEBUG
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device_printf(bridge,
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"bridge %d/%d/%d: latency timer %d -> %d\n",
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busno, slot, func, CS_READ(PCIR_SECLAT_1, 1), reg);
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#endif /* OFW_PCI_DEBUG */
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CS_WRITE(PCIR_SECLAT_1, reg, 1);
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} else {
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reg = CS_READ(PCIR_MINGNT, 1);
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if (reg != 0) {
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switch (clock) {
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case 33000000:
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reg *= 8;
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break;
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case 66000000:
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reg *= 4;
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break;
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}
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reg = min(reg, 255);
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} else
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reg = OFW_PCI_LATENCY;
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}
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#ifdef OFW_PCI_DEBUG
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device_printf(bridge, "device %d/%d/%d: latency timer %d -> %d\n",
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busno, slot, func, CS_READ(PCIR_LATTIMER, 1), reg);
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#endif /* OFW_PCI_DEBUG */
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CS_WRITE(PCIR_LATTIMER, reg, 1);
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/*
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* Compute a value to write into the cache line size register.
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* The role of the streaming cache is unclear in write invalidate
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* transfers, so it is made sure that it's line size is always
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* reached. Generally, the cache line size is fixed at 64 bytes
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* by Fireplane/Safari, JBus and UPA.
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*/
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CS_WRITE(PCIR_CACHELNSZ, STRBUF_LINESZ / sizeof(uint32_t), 1);
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#endif
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/*
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* Ensure that ALi M5229 report the actual content of PCIR_PROGIF
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* and that IDE I/O is force enabled. The former is done in order
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* to have unique behavior across revisions as some default to
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* hiding bits 4-6 for compliance with PCI 2.3. The latter is done
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* as at least revision 0xc8 requires the PCIM_CMD_PORTEN bypass
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* to be always enabled as otherwise even enabling PCIM_CMD_PORTEN
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* results in an instant data access trap on Fire-based machines.
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* Thus these quirks have to be handled before pci(4) adds the maps.
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* Note that for older revisions bit 0 of register 0x50 enables the
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* internal IDE function instead of force enabling IDE I/O.
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*/
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if ((CS_READ(PCIR_VENDOR, 2) == 0x10b9 &&
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CS_READ(PCIR_DEVICE, 2) == 0x5229))
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CS_WRITE(0x50, CS_READ(0x50, 1) | 0x3, 1);
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/*
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* The preset in the intline register is usually wrong. Reset
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* it to 255, so that the PCI code will reroute the interrupt if
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* needed.
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*/
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CS_WRITE(PCIR_INTLINE, PCI_INVALID_IRQ, 1);
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#undef CS_READ
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#undef CS_WRITE
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}
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static int
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ofw_pcibus_attach(device_t dev)
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{
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device_t pcib;
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struct ofw_pci_register pcir;
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struct ofw_pcibus_devinfo *dinfo;
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phandle_t node, child;
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uint32_t clock;
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u_int busno, domain, func, slot;
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pcib = device_get_parent(dev);
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domain = pcib_get_domain(dev);
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busno = pcib_get_bus(dev);
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if (bootverbose)
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device_printf(dev, "domain=%d, physical bus=%d\n",
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domain, busno);
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node = ofw_bus_get_node(dev);
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/*
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* Add the PCI side of the host-PCI bridge itself to the bus.
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* Note that we exclude the host-PCIe bridges here as these
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* have no configuration space implemented themselves.
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*/
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if (strcmp(device_get_name(device_get_parent(pcib)), "nexus") == 0 &&
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ofw_bus_get_type(pcib) != NULL &&
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strcmp(ofw_bus_get_type(pcib), OFW_TYPE_PCIE) != 0 &&
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(dinfo = (struct ofw_pcibus_devinfo *)pci_read_device(pcib,
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domain, busno, 0, 0, sizeof(*dinfo))) != NULL) {
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if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, node) != 0)
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pci_freecfg((struct pci_devinfo *)dinfo);
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else
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pci_add_child(dev, (struct pci_devinfo *)dinfo);
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}
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if (OF_getprop(ofw_bus_get_node(pcib), "clock-frequency", &clock,
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sizeof(clock)) == -1)
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clock = 33000000;
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for (child = OF_child(node); child != 0; child = OF_peer(child)) {
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if (OF_getprop(child, "reg", &pcir, sizeof(pcir)) == -1)
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continue;
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slot = OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi);
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func = OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi);
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/* Some OFW device trees contain dupes. */
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if (pci_find_dbsf(domain, busno, slot, func) != NULL)
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continue;
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ofw_pcibus_setup_device(pcib, clock, busno, slot, func);
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dinfo = (struct ofw_pcibus_devinfo *)pci_read_device(pcib,
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domain, busno, slot, func, sizeof(*dinfo));
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if (dinfo == NULL)
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continue;
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if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, child) !=
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0) {
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pci_freecfg((struct pci_devinfo *)dinfo);
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continue;
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}
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pci_add_child(dev, (struct pci_devinfo *)dinfo);
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}
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return (bus_generic_attach(dev));
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}
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static int
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ofw_pcibus_assign_interrupt(device_t dev, device_t child)
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{
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ofw_pci_intr_t intr;
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int isz;
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isz = OF_getprop(ofw_bus_get_node(child), "interrupts", &intr,
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sizeof(intr));
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if (isz != sizeof(intr)) {
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/* No property; our best guess is the intpin. */
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intr = pci_get_intpin(child);
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#ifndef SUN4V
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} else if (intr >= 255) {
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/*
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* A fully specified interrupt (including IGN), as present on
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* SPARCengine Ultra AX and E450. Extract the INO and return
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* it.
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*/
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return (INTINO(intr));
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#endif
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}
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/*
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* If we got intr from a property, it may or may not be an intpin.
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* For on-board devices, it frequently is not, and is completely out
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* of the valid intpin range. For PCI slots, it hopefully is,
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* otherwise we will have trouble interfacing with non-OFW buses
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* such as cardbus.
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* Since we cannot tell which it is without violating layering, we
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* will always use the route_interrupt method, and treat exceptions
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* on the level they become apparent.
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*/
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return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, intr));
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}
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static const struct ofw_bus_devinfo *
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ofw_pcibus_get_devinfo(device_t bus, device_t dev)
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{
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struct ofw_pcibus_devinfo *dinfo;
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dinfo = device_get_ivars(dev);
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return (&dinfo->opd_obdinfo);
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}
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static int
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ofw_pcibus_pnpinfo_str(device_t dev, device_t child, char *buf,
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size_t buflen)
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{
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pci_child_pnpinfo_str_method(dev, child, buf, buflen);
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if (ofw_bus_get_node(child) != -1) {
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strlcat(buf, " ", buflen); /* Separate info. */
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ofw_bus_gen_child_pnpinfo_str(dev, child, buf, buflen);
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}
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return (0);
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}
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